imx6qdl-sabrelite.dtsi 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0 OR X11
  2. /*
  3. * Copyright 2011 Freescale Semiconductor, Inc.
  4. * Copyright 2011 Linaro Ltd.
  5. *
  6. */
  7. #include <dt-bindings/clock/imx6qdl-clock.h>
  8. #include <dt-bindings/gpio/gpio.h>
  9. #include <dt-bindings/input/input.h>
  10. / {
  11. chosen {
  12. stdout-path = &uart2;
  13. };
  14. memory@10000000 {
  15. device_type = "memory";
  16. reg = <0x10000000 0x40000000>;
  17. };
  18. regulators {
  19. compatible = "simple-bus";
  20. #address-cells = <1>;
  21. #size-cells = <0>;
  22. reg_2p5v: regulator@0 {
  23. compatible = "regulator-fixed";
  24. reg = <0>;
  25. regulator-name = "2P5V";
  26. regulator-min-microvolt = <2500000>;
  27. regulator-max-microvolt = <2500000>;
  28. regulator-always-on;
  29. };
  30. reg_3p3v: regulator@1 {
  31. compatible = "regulator-fixed";
  32. reg = <1>;
  33. regulator-name = "3P3V";
  34. regulator-min-microvolt = <3300000>;
  35. regulator-max-microvolt = <3300000>;
  36. regulator-always-on;
  37. };
  38. reg_usb_otg_vbus: regulator@2 {
  39. compatible = "regulator-fixed";
  40. reg = <2>;
  41. regulator-name = "usb_otg_vbus";
  42. regulator-min-microvolt = <5000000>;
  43. regulator-max-microvolt = <5000000>;
  44. gpio = <&gpio3 22 0>;
  45. enable-active-high;
  46. };
  47. reg_can_xcvr: regulator@3 {
  48. compatible = "regulator-fixed";
  49. reg = <3>;
  50. regulator-name = "CAN XCVR";
  51. regulator-min-microvolt = <3300000>;
  52. regulator-max-microvolt = <3300000>;
  53. pinctrl-names = "default";
  54. pinctrl-0 = <&pinctrl_can_xcvr>;
  55. gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
  56. };
  57. reg_1p5v: regulator@4 {
  58. compatible = "regulator-fixed";
  59. reg = <4>;
  60. regulator-name = "1P5V";
  61. regulator-min-microvolt = <1500000>;
  62. regulator-max-microvolt = <1500000>;
  63. regulator-always-on;
  64. };
  65. reg_1p8v: regulator@5 {
  66. compatible = "regulator-fixed";
  67. reg = <5>;
  68. regulator-name = "1P8V";
  69. regulator-min-microvolt = <1800000>;
  70. regulator-max-microvolt = <1800000>;
  71. regulator-always-on;
  72. };
  73. reg_2p8v: regulator@6 {
  74. compatible = "regulator-fixed";
  75. reg = <6>;
  76. regulator-name = "2P8V";
  77. regulator-min-microvolt = <2800000>;
  78. regulator-max-microvolt = <2800000>;
  79. regulator-always-on;
  80. };
  81. reg_usb_h1_vbus: regulator@7 {
  82. compatible = "regulator-fixed";
  83. reg = <7>;
  84. pinctrl-names = "default";
  85. pinctrl-0 = <&pinctrl_usbh1>;
  86. regulator-name = "usb_h1_vbus";
  87. regulator-min-microvolt = <3300000>;
  88. regulator-max-microvolt = <3300000>;
  89. gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
  90. enable-active-high;
  91. };
  92. };
  93. mipi_xclk: mipi_xclk {
  94. compatible = "pwm-clock";
  95. #clock-cells = <0>;
  96. clock-frequency = <22000000>;
  97. clock-output-names = "mipi_pwm3";
  98. pwms = <&pwm3 0 45>; /* 1 / 45 ns = 22 MHz */
  99. status = "okay";
  100. };
  101. gpio-keys {
  102. compatible = "gpio-keys";
  103. pinctrl-names = "default";
  104. pinctrl-0 = <&pinctrl_gpio_keys>;
  105. power {
  106. label = "Power Button";
  107. gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
  108. linux,code = <KEY_POWER>;
  109. wakeup-source;
  110. };
  111. menu {
  112. label = "Menu";
  113. gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
  114. linux,code = <KEY_MENU>;
  115. };
  116. home {
  117. label = "Home";
  118. gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
  119. linux,code = <KEY_HOME>;
  120. };
  121. back {
  122. label = "Back";
  123. gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
  124. linux,code = <KEY_BACK>;
  125. };
  126. volume-up {
  127. label = "Volume Up";
  128. gpios = <&gpio7 13 GPIO_ACTIVE_LOW>;
  129. linux,code = <KEY_VOLUMEUP>;
  130. };
  131. volume-down {
  132. label = "Volume Down";
  133. gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
  134. linux,code = <KEY_VOLUMEDOWN>;
  135. };
  136. };
  137. sound {
  138. compatible = "fsl,imx6q-sabrelite-sgtl5000",
  139. "fsl,imx-audio-sgtl5000";
  140. model = "imx6q-sabrelite-sgtl5000";
  141. ssi-controller = <&ssi1>;
  142. audio-codec = <&codec>;
  143. audio-routing =
  144. "MIC_IN", "Mic Jack",
  145. "Mic Jack", "Mic Bias",
  146. "Headphone Jack", "HP_OUT";
  147. mux-int-port = <1>;
  148. mux-ext-port = <4>;
  149. };
  150. backlight_lcd: backlight-lcd {
  151. compatible = "pwm-backlight";
  152. pwms = <&pwm1 0 5000000>;
  153. brightness-levels = <0 4 8 16 32 64 128 255>;
  154. default-brightness-level = <7>;
  155. power-supply = <&reg_3p3v>;
  156. status = "okay";
  157. };
  158. backlight_lvds: backlight-lvds {
  159. compatible = "pwm-backlight";
  160. pwms = <&pwm4 0 5000000>;
  161. brightness-levels = <0 4 8 16 32 64 128 255>;
  162. default-brightness-level = <7>;
  163. power-supply = <&reg_3p3v>;
  164. status = "okay";
  165. };
  166. lcd_display: disp0 {
  167. compatible = "fsl,imx-parallel-display";
  168. #address-cells = <1>;
  169. #size-cells = <0>;
  170. interface-pix-fmt = "bgr666";
  171. pinctrl-names = "default";
  172. pinctrl-0 = <&pinctrl_j15>;
  173. status = "okay";
  174. port@0 {
  175. reg = <0>;
  176. lcd_display_in: endpoint {
  177. remote-endpoint = <&ipu1_di0_disp0>;
  178. };
  179. };
  180. port@1 {
  181. reg = <1>;
  182. lcd_display_out: endpoint {
  183. remote-endpoint = <&lcd_panel_in>;
  184. };
  185. };
  186. };
  187. panel-lcd {
  188. compatible = "okaya,rs800480t-7x0gp";
  189. backlight = <&backlight_lcd>;
  190. port {
  191. lcd_panel_in: endpoint {
  192. remote-endpoint = <&lcd_display_out>;
  193. };
  194. };
  195. };
  196. panel-lvds0 {
  197. compatible = "hannstar,hsd100pxn1";
  198. backlight = <&backlight_lvds>;
  199. port {
  200. panel_in: endpoint {
  201. remote-endpoint = <&lvds0_out>;
  202. };
  203. };
  204. };
  205. };
  206. &ipu1_csi0_from_ipu1_csi0_mux {
  207. bus-width = <8>;
  208. data-shift = <12>; /* Lines 19:12 used */
  209. hsync-active = <1>;
  210. vync-active = <1>;
  211. };
  212. &ipu1_csi0_mux_from_parallel_sensor {
  213. remote-endpoint = <&ov5642_to_ipu1_csi0_mux>;
  214. };
  215. &ipu1_csi0 {
  216. pinctrl-names = "default";
  217. pinctrl-0 = <&pinctrl_ipu1_csi0>;
  218. };
  219. &audmux {
  220. pinctrl-names = "default";
  221. pinctrl-0 = <&pinctrl_audmux>;
  222. status = "okay";
  223. };
  224. &can1 {
  225. pinctrl-names = "default";
  226. pinctrl-0 = <&pinctrl_can1>;
  227. xceiver-supply = <&reg_can_xcvr>;
  228. status = "okay";
  229. };
  230. &clks {
  231. assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
  232. <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
  233. assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
  234. <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
  235. };
  236. &ecspi1 {
  237. cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
  238. pinctrl-names = "default";
  239. pinctrl-0 = <&pinctrl_ecspi1>;
  240. status = "okay";
  241. flash: flash@0 {
  242. compatible = "sst,sst25vf016b", "jedec,spi-nor";
  243. spi-max-frequency = <20000000>;
  244. reg = <0>;
  245. };
  246. };
  247. &fec {
  248. pinctrl-names = "default";
  249. pinctrl-0 = <&pinctrl_enet>;
  250. phy-mode = "rgmii";
  251. phy-handle = <&ethphy>;
  252. phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
  253. status = "okay";
  254. mdio {
  255. #address-cells = <1>;
  256. #size-cells = <0>;
  257. ethphy: ethernet-phy {
  258. compatible = "ethernet-phy-ieee802.3-c22";
  259. txen-skew-ps = <0>;
  260. txc-skew-ps = <3000>;
  261. rxdv-skew-ps = <0>;
  262. rxc-skew-ps = <3000>;
  263. rxd0-skew-ps = <0>;
  264. rxd1-skew-ps = <0>;
  265. rxd2-skew-ps = <0>;
  266. rxd3-skew-ps = <0>;
  267. txd0-skew-ps = <0>;
  268. txd1-skew-ps = <0>;
  269. txd2-skew-ps = <0>;
  270. txd3-skew-ps = <0>;
  271. };
  272. };
  273. };
  274. &hdmi {
  275. ddc-i2c-bus = <&i2c2>;
  276. status = "okay";
  277. };
  278. &i2c1 {
  279. clock-frequency = <100000>;
  280. pinctrl-names = "default";
  281. pinctrl-0 = <&pinctrl_i2c1>;
  282. status = "okay";
  283. codec: sgtl5000@a {
  284. compatible = "fsl,sgtl5000";
  285. reg = <0x0a>;
  286. clocks = <&clks IMX6QDL_CLK_CKO>;
  287. VDDA-supply = <&reg_2p5v>;
  288. VDDIO-supply = <&reg_3p3v>;
  289. };
  290. };
  291. &i2c2 {
  292. clock-frequency = <100000>;
  293. pinctrl-names = "default";
  294. pinctrl-0 = <&pinctrl_i2c2>;
  295. status = "okay";
  296. ov5640: camera@40 {
  297. compatible = "ovti,ov5640";
  298. pinctrl-names = "default";
  299. pinctrl-0 = <&pinctrl_ov5640>;
  300. reg = <0x40>;
  301. clocks = <&mipi_xclk>;
  302. clock-names = "xclk";
  303. DOVDD-supply = <&reg_1p8v>;
  304. AVDD-supply = <&reg_2p8v>;
  305. DVDD-supply = <&reg_1p5v>;
  306. reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* NANDF_D5 */
  307. powerdown-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* NANDF_WP_B */
  308. port {
  309. ov5640_to_mipi_csi2: endpoint {
  310. remote-endpoint = <&mipi_csi2_in>;
  311. clock-lanes = <0>;
  312. data-lanes = <1 2>;
  313. };
  314. };
  315. };
  316. ov5642: camera@42 {
  317. compatible = "ovti,ov5642";
  318. pinctrl-names = "default";
  319. pinctrl-0 = <&pinctrl_ov5642>;
  320. clocks = <&clks IMX6QDL_CLK_CKO2>;
  321. clock-names = "xclk";
  322. reg = <0x42>;
  323. reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
  324. powerdown-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
  325. gp-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
  326. status = "disabled";
  327. port {
  328. ov5642_to_ipu1_csi0_mux: endpoint {
  329. remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
  330. bus-width = <8>;
  331. hsync-active = <1>;
  332. vsync-active = <1>;
  333. };
  334. };
  335. };
  336. };
  337. &i2c3 {
  338. clock-frequency = <100000>;
  339. pinctrl-names = "default";
  340. pinctrl-0 = <&pinctrl_i2c3>;
  341. status = "okay";
  342. };
  343. &iomuxc {
  344. pinctrl-names = "default";
  345. pinctrl-0 = <&pinctrl_hog>;
  346. imx6q-sabrelite {
  347. pinctrl_hog: hoggrp {
  348. fsl,pins = <
  349. /* SGTL5000 sys_mclk */
  350. MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0
  351. >;
  352. };
  353. pinctrl_audmux: audmuxgrp {
  354. fsl,pins = <
  355. MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
  356. MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
  357. MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
  358. MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
  359. >;
  360. };
  361. pinctrl_can1: can1grp {
  362. fsl,pins = <
  363. MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0
  364. MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0
  365. >;
  366. };
  367. pinctrl_can_xcvr: can-xcvrgrp {
  368. fsl,pins = <
  369. /* Flexcan XCVR enable */
  370. MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
  371. >;
  372. };
  373. pinctrl_ecspi1: ecspi1grp {
  374. fsl,pins = <
  375. MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
  376. MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
  377. MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
  378. MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 /* CS */
  379. >;
  380. };
  381. pinctrl_enet: enetgrp {
  382. fsl,pins = <
  383. MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
  384. MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
  385. MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030
  386. MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030
  387. MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030
  388. MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030
  389. MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030
  390. MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030
  391. MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
  392. MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
  393. MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
  394. MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
  395. MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
  396. MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
  397. MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
  398. /* Phy reset */
  399. MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x000b0
  400. >;
  401. };
  402. pinctrl_gpio_keys: gpio-keysgrp {
  403. fsl,pins = <
  404. /* Power Button */
  405. MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
  406. /* Menu Button */
  407. MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
  408. /* Home Button */
  409. MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0
  410. /* Back Button */
  411. MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
  412. /* Volume Up Button */
  413. MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0
  414. /* Volume Down Button */
  415. MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
  416. >;
  417. };
  418. pinctrl_i2c1: i2c1grp {
  419. fsl,pins = <
  420. MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
  421. MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
  422. >;
  423. };
  424. pinctrl_i2c2: i2c2grp {
  425. fsl,pins = <
  426. MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
  427. MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  428. >;
  429. };
  430. pinctrl_i2c3: i2c3grp {
  431. fsl,pins = <
  432. MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
  433. MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
  434. >;
  435. };
  436. pinctrl_ipu1_csi0: ipu1csi0grp {
  437. fsl,pins = <
  438. MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
  439. MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
  440. MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
  441. MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
  442. MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
  443. MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
  444. MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
  445. MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
  446. MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
  447. MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
  448. MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
  449. MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x1b0b0
  450. >;
  451. };
  452. pinctrl_j15: j15grp {
  453. fsl,pins = <
  454. MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
  455. MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
  456. MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
  457. MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
  458. MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
  459. MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
  460. MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
  461. MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
  462. MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
  463. MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
  464. MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
  465. MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
  466. MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
  467. MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
  468. MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
  469. MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
  470. MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
  471. MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
  472. MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
  473. MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
  474. MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
  475. MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
  476. MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
  477. MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
  478. MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
  479. MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
  480. MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
  481. MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
  482. >;
  483. };
  484. pinctrl_ov5640: ov5640grp {
  485. fsl,pins = <
  486. MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x000b0
  487. MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b0
  488. >;
  489. };
  490. pinctrl_ov5642: ov5642grp {
  491. fsl,pins = <
  492. MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
  493. MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0
  494. MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x130b0
  495. MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0
  496. >;
  497. };
  498. pinctrl_pwm1: pwm1grp {
  499. fsl,pins = <
  500. MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
  501. >;
  502. };
  503. pinctrl_pwm3: pwm3grp {
  504. fsl,pins = <
  505. MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
  506. >;
  507. };
  508. pinctrl_pwm4: pwm4grp {
  509. fsl,pins = <
  510. MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
  511. >;
  512. };
  513. pinctrl_uart1: uart1grp {
  514. fsl,pins = <
  515. MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
  516. MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
  517. >;
  518. };
  519. pinctrl_uart2: uart2grp {
  520. fsl,pins = <
  521. MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
  522. MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
  523. >;
  524. };
  525. pinctrl_usbh1: usbh1grp {
  526. fsl,pins = <
  527. MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0
  528. >;
  529. };
  530. pinctrl_usbotg: usbotggrp {
  531. fsl,pins = <
  532. MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
  533. MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
  534. /* power enable, high active */
  535. MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0
  536. >;
  537. };
  538. pinctrl_usdhc3: usdhc3grp {
  539. fsl,pins = <
  540. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
  541. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
  542. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
  543. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
  544. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
  545. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
  546. MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */
  547. MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* WP */
  548. >;
  549. };
  550. pinctrl_usdhc4: usdhc4grp {
  551. fsl,pins = <
  552. MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
  553. MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
  554. MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
  555. MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
  556. MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
  557. MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
  558. MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 /* CD */
  559. >;
  560. };
  561. };
  562. };
  563. &ipu1_di0_disp0 {
  564. remote-endpoint = <&lcd_display_in>;
  565. };
  566. &ldb {
  567. status = "okay";
  568. lvds-channel@0 {
  569. status = "okay";
  570. port@4 {
  571. reg = <4>;
  572. lvds0_out: endpoint {
  573. remote-endpoint = <&panel_in>;
  574. };
  575. };
  576. };
  577. };
  578. &pcie {
  579. status = "okay";
  580. };
  581. &pwm1 {
  582. #pwm-cells = <2>;
  583. pinctrl-names = "default";
  584. pinctrl-0 = <&pinctrl_pwm1>;
  585. status = "okay";
  586. };
  587. &pwm3 {
  588. #pwm-cells = <2>;
  589. pinctrl-names = "default";
  590. pinctrl-0 = <&pinctrl_pwm3>;
  591. status = "okay";
  592. };
  593. &pwm4 {
  594. #pwm-cells = <2>;
  595. pinctrl-names = "default";
  596. pinctrl-0 = <&pinctrl_pwm4>;
  597. status = "okay";
  598. };
  599. &ssi1 {
  600. status = "okay";
  601. };
  602. &uart1 {
  603. pinctrl-names = "default";
  604. pinctrl-0 = <&pinctrl_uart1>;
  605. status = "okay";
  606. };
  607. &uart2 {
  608. pinctrl-names = "default";
  609. pinctrl-0 = <&pinctrl_uart2>;
  610. status = "okay";
  611. };
  612. &usbh1 {
  613. vbus-supply = <&reg_usb_h1_vbus>;
  614. status = "okay";
  615. };
  616. &usbotg {
  617. vbus-supply = <&reg_usb_otg_vbus>;
  618. pinctrl-names = "default";
  619. pinctrl-0 = <&pinctrl_usbotg>;
  620. disable-over-current;
  621. status = "okay";
  622. };
  623. &usdhc3 {
  624. pinctrl-names = "default";
  625. pinctrl-0 = <&pinctrl_usdhc3>;
  626. cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
  627. wp-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
  628. vmmc-supply = <&reg_3p3v>;
  629. status = "okay";
  630. };
  631. &usdhc4 {
  632. pinctrl-names = "default";
  633. pinctrl-0 = <&pinctrl_usdhc4>;
  634. cd-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
  635. vmmc-supply = <&reg_3p3v>;
  636. status = "okay";
  637. };
  638. &mipi_csi {
  639. status = "okay";
  640. port@0 {
  641. reg = <0>;
  642. mipi_csi2_in: endpoint {
  643. remote-endpoint = <&ov5640_to_mipi_csi2>;
  644. clock-lanes = <0>;
  645. data-lanes = <1 2>;
  646. };
  647. };
  648. };