imx6qdl-nitrogen6_max.dtsi 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0 OR X11
  2. /*
  3. * Copyright 2015 Boundary Devices, Inc.
  4. */
  5. #include <dt-bindings/gpio/gpio.h>
  6. #include <dt-bindings/input/input.h>
  7. / {
  8. chosen {
  9. stdout-path = &uart2;
  10. };
  11. memory@10000000 {
  12. device_type = "memory";
  13. reg = <0x10000000 0xF0000000>;
  14. };
  15. regulators {
  16. compatible = "simple-bus";
  17. #address-cells = <1>;
  18. #size-cells = <0>;
  19. reg_1p8v: regulator@0 {
  20. compatible = "regulator-fixed";
  21. reg = <0>;
  22. regulator-name = "1P8V";
  23. regulator-min-microvolt = <1800000>;
  24. regulator-max-microvolt = <1800000>;
  25. regulator-always-on;
  26. };
  27. reg_2p5v: regulator@1 {
  28. compatible = "regulator-fixed";
  29. reg = <1>;
  30. regulator-name = "2P5V";
  31. regulator-min-microvolt = <2500000>;
  32. regulator-max-microvolt = <2500000>;
  33. regulator-always-on;
  34. };
  35. reg_3p3v: regulator@2 {
  36. compatible = "regulator-fixed";
  37. reg = <2>;
  38. regulator-name = "3P3V";
  39. regulator-min-microvolt = <3300000>;
  40. regulator-max-microvolt = <3300000>;
  41. regulator-always-on;
  42. };
  43. reg_usb_otg_vbus: regulator@3 {
  44. compatible = "regulator-fixed";
  45. reg = <3>;
  46. regulator-name = "usb_otg_vbus";
  47. regulator-min-microvolt = <5000000>;
  48. regulator-max-microvolt = <5000000>;
  49. gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
  50. enable-active-high;
  51. };
  52. reg_usb_h1_vbus: regulator@4 {
  53. compatible = "regulator-fixed";
  54. reg = <4>;
  55. pinctrl-names = "default";
  56. pinctrl-0 = <&pinctrl_usbh1>;
  57. regulator-name = "usb_h1_vbus";
  58. regulator-min-microvolt = <3300000>;
  59. regulator-max-microvolt = <3300000>;
  60. gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
  61. enable-active-high;
  62. };
  63. reg_wlan_vmmc: regulator@5 {
  64. compatible = "regulator-fixed";
  65. reg = <5>;
  66. pinctrl-names = "default";
  67. pinctrl-0 = <&pinctrl_wlan_vmmc>;
  68. regulator-name = "reg_wlan_vmmc";
  69. regulator-min-microvolt = <3300000>;
  70. regulator-max-microvolt = <3300000>;
  71. gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>;
  72. startup-delay-us = <70000>;
  73. enable-active-high;
  74. };
  75. reg_can_xcvr: regulator@6 {
  76. compatible = "regulator-fixed";
  77. reg = <6>;
  78. regulator-name = "CAN XCVR";
  79. regulator-min-microvolt = <3300000>;
  80. regulator-max-microvolt = <3300000>;
  81. pinctrl-names = "default";
  82. pinctrl-0 = <&pinctrl_can_xcvr>;
  83. gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
  84. };
  85. };
  86. gpio-keys {
  87. compatible = "gpio-keys";
  88. pinctrl-names = "default";
  89. pinctrl-0 = <&pinctrl_gpio_keys>;
  90. power {
  91. label = "Power Button";
  92. gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
  93. linux,code = <KEY_POWER>;
  94. wakeup-source;
  95. };
  96. menu {
  97. label = "Menu";
  98. gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
  99. linux,code = <KEY_MENU>;
  100. };
  101. home {
  102. label = "Home";
  103. gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
  104. linux,code = <KEY_HOME>;
  105. };
  106. back {
  107. label = "Back";
  108. gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
  109. linux,code = <KEY_BACK>;
  110. };
  111. volume-up {
  112. label = "Volume Up";
  113. gpios = <&gpio7 13 GPIO_ACTIVE_LOW>;
  114. linux,code = <KEY_VOLUMEUP>;
  115. };
  116. volume-down {
  117. label = "Volume Down";
  118. gpios = <&gpio7 1 GPIO_ACTIVE_LOW>;
  119. linux,code = <KEY_VOLUMEDOWN>;
  120. };
  121. };
  122. i2c2mux {
  123. compatible = "i2c-mux-gpio";
  124. pinctrl-names = "default";
  125. pinctrl-0 = <&pinctrl_i2c2mux>;
  126. #address-cells = <1>;
  127. #size-cells = <0>;
  128. mux-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH
  129. &gpio4 15 GPIO_ACTIVE_HIGH>;
  130. i2c-parent = <&i2c2>;
  131. idle-state = <0>;
  132. i2c2mux@1 {
  133. reg = <1>;
  134. #address-cells = <1>;
  135. #size-cells = <0>;
  136. };
  137. i2c2mux@2 {
  138. reg = <2>;
  139. #address-cells = <1>;
  140. #size-cells = <0>;
  141. };
  142. };
  143. i2c3mux {
  144. compatible = "i2c-mux-gpio";
  145. pinctrl-names = "default";
  146. pinctrl-0 = <&pinctrl_i2c3mux>;
  147. #address-cells = <1>;
  148. #size-cells = <0>;
  149. mux-gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>;
  150. i2c-parent = <&i2c3>;
  151. idle-state = <0>;
  152. i2c3mux@1 {
  153. reg = <1>;
  154. #address-cells = <1>;
  155. #size-cells = <0>;
  156. };
  157. };
  158. leds {
  159. compatible = "gpio-leds";
  160. led-speaker-enable {
  161. gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
  162. retain-state-suspended;
  163. default-state = "off";
  164. };
  165. led-ttymxc4-rs232 {
  166. gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>;
  167. retain-state-suspended;
  168. default-state = "on";
  169. };
  170. };
  171. backlight_lcd: backlight-lcd {
  172. compatible = "pwm-backlight";
  173. pwms = <&pwm1 0 5000000>;
  174. brightness-levels = <0 4 8 16 32 64 128 255>;
  175. default-brightness-level = <7>;
  176. power-supply = <&reg_3p3v>;
  177. status = "okay";
  178. };
  179. backlight_lvds0: backlight-lvds0 {
  180. compatible = "pwm-backlight";
  181. pwms = <&pwm4 0 5000000>;
  182. brightness-levels = <0 4 8 16 32 64 128 255>;
  183. default-brightness-level = <7>;
  184. power-supply = <&reg_3p3v>;
  185. status = "okay";
  186. };
  187. backlight_lvds1: backlight-lvds1 {
  188. compatible = "pwm-backlight";
  189. pwms = <&pwm2 0 5000000>;
  190. brightness-levels = <0 4 8 16 32 64 128 255>;
  191. default-brightness-level = <7>;
  192. power-supply = <&reg_3p3v>;
  193. status = "okay";
  194. };
  195. lcd_display: disp0 {
  196. compatible = "fsl,imx-parallel-display";
  197. #address-cells = <1>;
  198. #size-cells = <0>;
  199. interface-pix-fmt = "bgr666";
  200. pinctrl-names = "default";
  201. pinctrl-0 = <&pinctrl_j15>;
  202. status = "okay";
  203. port@0 {
  204. reg = <0>;
  205. lcd_display_in: endpoint {
  206. remote-endpoint = <&ipu1_di0_disp0>;
  207. };
  208. };
  209. port@1 {
  210. reg = <1>;
  211. lcd_display_out: endpoint {
  212. remote-endpoint = <&lcd_panel_in>;
  213. };
  214. };
  215. };
  216. panel-lcd {
  217. compatible = "okaya,rs800480t-7x0gp";
  218. backlight = <&backlight_lcd>;
  219. port {
  220. lcd_panel_in: endpoint {
  221. remote-endpoint = <&lcd_display_out>;
  222. };
  223. };
  224. };
  225. panel-lvds0 {
  226. compatible = "hannstar,hsd100pxn1";
  227. backlight = <&backlight_lvds0>;
  228. port {
  229. panel_in_lvds0: endpoint {
  230. remote-endpoint = <&lvds0_out>;
  231. };
  232. };
  233. };
  234. panel-lvds1 {
  235. compatible = "hannstar,hsd100pxn1";
  236. backlight = <&backlight_lvds1>;
  237. port {
  238. panel_in_lvds1: endpoint {
  239. remote-endpoint = <&lvds1_out>;
  240. };
  241. };
  242. };
  243. sound {
  244. compatible = "fsl,imx6q-nitrogen6_max-sgtl5000",
  245. "fsl,imx-audio-sgtl5000";
  246. model = "imx6q-nitrogen6_max-sgtl5000";
  247. ssi-controller = <&ssi1>;
  248. audio-codec = <&codec>;
  249. audio-routing =
  250. "MIC_IN", "Mic Jack",
  251. "Mic Jack", "Mic Bias",
  252. "Headphone Jack", "HP_OUT";
  253. mux-int-port = <1>;
  254. mux-ext-port = <3>;
  255. };
  256. };
  257. &audmux {
  258. pinctrl-names = "default";
  259. pinctrl-0 = <&pinctrl_audmux>;
  260. status = "okay";
  261. };
  262. &can1 {
  263. pinctrl-names = "default";
  264. pinctrl-0 = <&pinctrl_can1>;
  265. xceiver-supply = <&reg_can_xcvr>;
  266. status = "okay";
  267. };
  268. &clks {
  269. assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
  270. <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
  271. assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
  272. <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
  273. };
  274. &ecspi1 {
  275. cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
  276. pinctrl-names = "default";
  277. pinctrl-0 = <&pinctrl_ecspi1>;
  278. status = "okay";
  279. flash: flash@0 {
  280. compatible = "microchip,sst25vf016b";
  281. spi-max-frequency = <20000000>;
  282. reg = <0>;
  283. };
  284. };
  285. &fec {
  286. pinctrl-names = "default";
  287. pinctrl-0 = <&pinctrl_enet>;
  288. phy-mode = "rgmii";
  289. phy-handle = <&ethphy>;
  290. phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
  291. /delete-property/ interrupts;
  292. interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
  293. <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
  294. fsl,err006687-workaround-present;
  295. status = "okay";
  296. mdio {
  297. #address-cells = <1>;
  298. #size-cells = <0>;
  299. ethphy: ethernet-phy {
  300. compatible = "ethernet-phy-ieee802.3-c22";
  301. txen-skew-ps = <0>;
  302. txc-skew-ps = <3000>;
  303. rxdv-skew-ps = <0>;
  304. rxc-skew-ps = <3000>;
  305. rxd0-skew-ps = <0>;
  306. rxd1-skew-ps = <0>;
  307. rxd2-skew-ps = <0>;
  308. rxd3-skew-ps = <0>;
  309. txd0-skew-ps = <0>;
  310. txd1-skew-ps = <0>;
  311. txd2-skew-ps = <0>;
  312. txd3-skew-ps = <0>;
  313. };
  314. };
  315. };
  316. &hdmi {
  317. ddc-i2c-bus = <&i2c2>;
  318. status = "okay";
  319. };
  320. &i2c1 {
  321. clock-frequency = <100000>;
  322. pinctrl-names = "default";
  323. pinctrl-0 = <&pinctrl_i2c1>;
  324. status = "okay";
  325. codec: sgtl5000@a {
  326. compatible = "fsl,sgtl5000";
  327. pinctrl-names = "default";
  328. pinctrl-0 = <&pinctrl_sgtl5000>;
  329. reg = <0x0a>;
  330. clocks = <&clks IMX6QDL_CLK_CKO>;
  331. VDDA-supply = <&reg_2p5v>;
  332. VDDIO-supply = <&reg_3p3v>;
  333. };
  334. rtc: rtc@68 {
  335. compatible = "microcrystal,rv4162";
  336. pinctrl-names = "default";
  337. pinctrl-0 = <&pinctrl_rv4162>;
  338. reg = <0x68>;
  339. interrupts-extended = <&gpio4 6 IRQ_TYPE_LEVEL_LOW>;
  340. };
  341. };
  342. &i2c2 {
  343. clock-frequency = <100000>;
  344. pinctrl-names = "default";
  345. pinctrl-0 = <&pinctrl_i2c2>;
  346. status = "okay";
  347. };
  348. &i2c3 {
  349. clock-frequency = <100000>;
  350. pinctrl-names = "default";
  351. pinctrl-0 = <&pinctrl_i2c3>;
  352. status = "okay";
  353. touchscreen@4 {
  354. compatible = "eeti,egalax_ts";
  355. reg = <0x04>;
  356. interrupt-parent = <&gpio1>;
  357. interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
  358. wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
  359. };
  360. touchscreen@38 {
  361. compatible = "edt,edt-ft5x06";
  362. reg = <0x38>;
  363. interrupt-parent = <&gpio1>;
  364. interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
  365. wakeup-source;
  366. };
  367. };
  368. &iomuxc {
  369. imx6q-nitrogen6-max {
  370. pinctrl_audmux: audmuxgrp {
  371. fsl,pins = <
  372. MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
  373. MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
  374. MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
  375. MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
  376. >;
  377. };
  378. pinctrl_can1: can1grp {
  379. fsl,pins = <
  380. MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0
  381. MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0
  382. >;
  383. };
  384. pinctrl_can_xcvr: can-xcvrgrp {
  385. fsl,pins = <
  386. /* Flexcan XCVR enable */
  387. MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
  388. >;
  389. };
  390. pinctrl_ecspi1: ecspi1grp {
  391. fsl,pins = <
  392. MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
  393. MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
  394. MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
  395. MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1
  396. >;
  397. };
  398. pinctrl_enet: enetgrp {
  399. fsl,pins = <
  400. MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
  401. MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
  402. MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030
  403. MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030
  404. MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030
  405. MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030
  406. MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030
  407. MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030
  408. MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
  409. MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
  410. MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
  411. MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
  412. MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
  413. MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
  414. MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
  415. /* Phy reset */
  416. MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x0f0b0
  417. MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
  418. MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
  419. >;
  420. };
  421. pinctrl_gpio_keys: gpio-keysgrp {
  422. fsl,pins = <
  423. /* Power Button */
  424. MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
  425. /* Menu Button */
  426. MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
  427. /* Home Button */
  428. MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0
  429. /* Back Button */
  430. MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
  431. /* Volume Up Button */
  432. MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0
  433. /* Volume Down Button */
  434. MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0
  435. >;
  436. };
  437. pinctrl_i2c1: i2c1grp {
  438. fsl,pins = <
  439. MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
  440. MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
  441. >;
  442. };
  443. pinctrl_i2c2: i2c2grp {
  444. fsl,pins = <
  445. MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
  446. MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  447. >;
  448. };
  449. pinctrl_i2c2mux: i2c2muxgrp {
  450. fsl,pins = <
  451. /* ov5642 camera i2c enable */
  452. MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x000b0
  453. /* ov5640_mipi camera i2c enable */
  454. MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b0
  455. >;
  456. };
  457. pinctrl_i2c3: i2c3grp {
  458. fsl,pins = <
  459. MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
  460. MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
  461. MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
  462. >;
  463. };
  464. pinctrl_i2c3mux: i2c3muxgrp {
  465. fsl,pins = <
  466. /* PCIe I2C enable */
  467. MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x000b0
  468. >;
  469. };
  470. pinctrl_j15: j15grp {
  471. fsl,pins = <
  472. MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
  473. MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
  474. MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
  475. MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
  476. MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
  477. MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
  478. MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
  479. MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
  480. MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
  481. MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
  482. MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
  483. MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
  484. MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
  485. MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
  486. MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
  487. MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
  488. MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
  489. MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
  490. MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
  491. MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
  492. MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
  493. MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
  494. MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
  495. MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
  496. MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
  497. MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
  498. MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
  499. MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
  500. >;
  501. };
  502. pinctrl_pcie: pciegrp {
  503. fsl,pins = <
  504. /* PCIe reset */
  505. MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x000b0
  506. >;
  507. };
  508. pinctrl_pwm1: pwm1grp {
  509. fsl,pins = <
  510. MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
  511. >;
  512. };
  513. pinctrl_pwm2: pwm2grp {
  514. fsl,pins = <
  515. MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
  516. >;
  517. };
  518. pinctrl_pwm3: pwm3grp {
  519. fsl,pins = <
  520. MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
  521. >;
  522. };
  523. pinctrl_pwm4: pwm4grp {
  524. fsl,pins = <
  525. MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
  526. >;
  527. };
  528. pinctrl_rv4162: rv4162grp {
  529. fsl,pins = <
  530. MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
  531. >;
  532. };
  533. pinctrl_sgtl5000: sgtl5000grp {
  534. fsl,pins = <
  535. MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0
  536. MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0
  537. MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
  538. >;
  539. };
  540. pinctrl_uart1: uart1grp {
  541. fsl,pins = <
  542. MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
  543. MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
  544. >;
  545. };
  546. pinctrl_uart2: uart2grp {
  547. fsl,pins = <
  548. MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
  549. MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
  550. >;
  551. };
  552. pinctrl_uart5: uart5grp {
  553. fsl,pins = <
  554. MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x130b1
  555. MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x030b1
  556. /* RS485 RX Enable: pull up */
  557. MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b1
  558. /* RS485 DEN: pull down */
  559. MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x030b1
  560. /* RS485/!RS232 Select: pull down (rs232) */
  561. MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x030b1
  562. /* ON: pull down */
  563. MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x030b1
  564. >;
  565. };
  566. pinctrl_usbh1: usbh1grp {
  567. fsl,pins = <
  568. MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0b0b0
  569. >;
  570. };
  571. pinctrl_usbotg: usbotggrp {
  572. fsl,pins = <
  573. MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
  574. MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
  575. /* power enable, high active */
  576. MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0
  577. >;
  578. };
  579. pinctrl_usdhc2: usdhc2grp {
  580. fsl,pins = <
  581. MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
  582. MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
  583. MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
  584. MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
  585. MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
  586. MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
  587. >;
  588. };
  589. pinctrl_usdhc3: usdhc3grp {
  590. fsl,pins = <
  591. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
  592. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
  593. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
  594. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
  595. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
  596. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
  597. MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x100b0
  598. MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0
  599. >;
  600. };
  601. pinctrl_usdhc4: usdhc4grp {
  602. fsl,pins = <
  603. MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
  604. MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
  605. MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
  606. MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
  607. MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
  608. MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
  609. MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
  610. MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
  611. MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
  612. MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
  613. >;
  614. };
  615. pinctrl_wlan_vmmc: wlan-vmmcgrp {
  616. fsl,pins = <
  617. MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x100b0
  618. MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0
  619. MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x000b0
  620. MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0
  621. >;
  622. };
  623. };
  624. };
  625. &ipu1_di0_disp0 {
  626. remote-endpoint = <&lcd_display_in>;
  627. };
  628. &ldb {
  629. status = "okay";
  630. lvds-channel@0 {
  631. status = "okay";
  632. port@4 {
  633. reg = <4>;
  634. lvds0_out: endpoint {
  635. remote-endpoint = <&panel_in_lvds0>;
  636. };
  637. };
  638. };
  639. lvds-channel@1 {
  640. status = "okay";
  641. port@4 {
  642. reg = <4>;
  643. lvds1_out: endpoint {
  644. remote-endpoint = <&panel_in_lvds1>;
  645. };
  646. };
  647. };
  648. };
  649. &pcie {
  650. pinctrl-names = "default";
  651. pinctrl-0 = <&pinctrl_pcie>;
  652. reset-gpio = <&gpio6 31 GPIO_ACTIVE_LOW>;
  653. status = "okay";
  654. };
  655. &pwm1 {
  656. #pwm-cells = <2>;
  657. pinctrl-names = "default";
  658. pinctrl-0 = <&pinctrl_pwm1>;
  659. status = "okay";
  660. };
  661. &pwm2 {
  662. #pwm-cells = <2>;
  663. pinctrl-names = "default";
  664. pinctrl-0 = <&pinctrl_pwm2>;
  665. status = "okay";
  666. };
  667. &pwm3 {
  668. pinctrl-names = "default";
  669. pinctrl-0 = <&pinctrl_pwm3>;
  670. status = "okay";
  671. };
  672. &pwm4 {
  673. #pwm-cells = <2>;
  674. pinctrl-names = "default";
  675. pinctrl-0 = <&pinctrl_pwm4>;
  676. status = "okay";
  677. };
  678. &ssi1 {
  679. status = "okay";
  680. };
  681. &uart1 {
  682. pinctrl-names = "default";
  683. pinctrl-0 = <&pinctrl_uart1>;
  684. status = "okay";
  685. };
  686. &uart2 {
  687. pinctrl-names = "default";
  688. pinctrl-0 = <&pinctrl_uart2>;
  689. status = "okay";
  690. };
  691. &uart5 {
  692. pinctrl-names = "default";
  693. pinctrl-0 = <&pinctrl_uart5>;
  694. status = "okay";
  695. };
  696. &usbh1 {
  697. vbus-supply = <&reg_usb_h1_vbus>;
  698. status = "okay";
  699. };
  700. &usbotg {
  701. vbus-supply = <&reg_usb_otg_vbus>;
  702. pinctrl-names = "default";
  703. pinctrl-0 = <&pinctrl_usbotg>;
  704. disable-over-current;
  705. status = "okay";
  706. };
  707. &usdhc2 {
  708. pinctrl-names = "default";
  709. pinctrl-0 = <&pinctrl_usdhc2>;
  710. bus-width = <4>;
  711. non-removable;
  712. vmmc-supply = <&reg_wlan_vmmc>;
  713. cap-power-off-card;
  714. keep-power-in-suspend;
  715. status = "okay";
  716. #address-cells = <1>;
  717. #size-cells = <0>;
  718. wlcore: wlcore@2 {
  719. compatible = "ti,wl1271";
  720. reg = <2>;
  721. interrupt-parent = <&gpio6>;
  722. interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
  723. ref-clock-frequency = <38400000>;
  724. };
  725. };
  726. &usdhc3 {
  727. pinctrl-names = "default";
  728. pinctrl-0 = <&pinctrl_usdhc3>;
  729. cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
  730. bus-width = <4>;
  731. vmmc-supply = <&reg_3p3v>;
  732. status = "okay";
  733. };
  734. &usdhc4 {
  735. pinctrl-names = "default";
  736. pinctrl-0 = <&pinctrl_usdhc4>;
  737. bus-width = <8>;
  738. non-removable;
  739. vmmc-supply = <&reg_1p8v>;
  740. keep-power-in-suspend;
  741. status = "okay";
  742. };