imx6qdl-gw5903.dtsi 19 KB

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  1. /*
  2. * Copyright 2017 Gateworks Corporation
  3. *
  4. * This file is dual-licensed: you can use it either under the terms
  5. * of the GPL or the X11 license, at your option. Note that this dual
  6. * licensing only applies to this file, and not this project as a
  7. * whole.
  8. *
  9. * a) This file is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of
  12. * the License, or (at your option) any later version.
  13. *
  14. * This file is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public
  20. * License along with this file; if not, write to the Free
  21. * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  22. * MA 02110-1301 USA
  23. *
  24. * Or, alternatively,
  25. *
  26. * b) Permission is hereby granted, free of charge, to any person
  27. * obtaining a copy of this software and associated documentation
  28. * files (the "Software"), to deal in the Software without
  29. * restriction, including without limitation the rights to use,
  30. * copy, modify, merge, publish, distribute, sublicense, and/or
  31. * sell copies of the Software, and to permit persons to whom the
  32. * Software is furnished to do so, subject to the following
  33. * conditions:
  34. *
  35. * The above copyright notice and this permission notice shall be
  36. * included in all copies or substantial portions of the Software.
  37. *
  38. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40. * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42. * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  43. * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45. * OTHER DEALINGS IN THE SOFTWARE.
  46. */
  47. #include <dt-bindings/gpio/gpio.h>
  48. #include <dt-bindings/input/linux-event-codes.h>
  49. #include <dt-bindings/interrupt-controller/irq.h>
  50. / {
  51. chosen {
  52. stdout-path = &uart2;
  53. };
  54. backlight {
  55. compatible = "pwm-backlight";
  56. pwms = <&pwm1 0 5000000>;
  57. brightness-levels = <
  58. 0 1 2 3 4 5 6 7 8 9
  59. 10 11 12 13 14 15 16 17 18 19
  60. 20 21 22 23 24 25 26 27 28 29
  61. 30 31 32 33 34 35 36 37 38 39
  62. 40 41 42 43 44 45 46 47 48 49
  63. 50 51 52 53 54 55 56 57 58 59
  64. 60 61 62 63 64 65 66 67 68 69
  65. 70 71 72 73 74 75 76 77 78 79
  66. 80 81 82 83 84 85 86 87 88 89
  67. 90 91 92 93 94 95 96 97 98 99
  68. 100
  69. >;
  70. default-brightness-level = <100>;
  71. };
  72. gpio-keys {
  73. compatible = "gpio-keys";
  74. user-pb {
  75. label = "user_pb";
  76. gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
  77. linux,code = <BTN_0>;
  78. };
  79. user-pb1x {
  80. label = "user_pb1x";
  81. linux,code = <BTN_1>;
  82. interrupt-parent = <&gsc>;
  83. interrupts = <0>;
  84. };
  85. key-erased {
  86. label = "key-erased";
  87. linux,code = <BTN_2>;
  88. interrupt-parent = <&gsc>;
  89. interrupts = <1>;
  90. };
  91. eeprom-wp {
  92. label = "eeprom_wp";
  93. linux,code = <BTN_3>;
  94. interrupt-parent = <&gsc>;
  95. interrupts = <2>;
  96. };
  97. tamper {
  98. label = "tamper";
  99. linux,code = <BTN_4>;
  100. interrupt-parent = <&gsc>;
  101. interrupts = <5>;
  102. };
  103. switch-hold {
  104. label = "switch_hold";
  105. linux,code = <BTN_5>;
  106. interrupt-parent = <&gsc>;
  107. interrupts = <7>;
  108. };
  109. };
  110. leds {
  111. compatible = "gpio-leds";
  112. pinctrl-names = "default";
  113. pinctrl-0 = <&pinctrl_gpio_leds>;
  114. led0: led-user1 {
  115. label = "user1";
  116. gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
  117. default-state = "off";
  118. };
  119. };
  120. memory@10000000 {
  121. device_type = "memory";
  122. reg = <0x10000000 0x40000000>;
  123. };
  124. reg_5p0v: regulator-5p0v {
  125. compatible = "regulator-fixed";
  126. regulator-name = "5P0V";
  127. regulator-min-microvolt = <5000000>;
  128. regulator-max-microvolt = <5000000>;
  129. regulator-always-on;
  130. };
  131. reg_3p3v: regulator-3p3v {
  132. compatible = "regulator-fixed";
  133. regulator-name = "3P3V";
  134. regulator-min-microvolt = <3300000>;
  135. regulator-max-microvolt = <3300000>;
  136. regulator-always-on;
  137. };
  138. reg_2p5v: regulator-2p5v {
  139. compatible = "regulator-fixed";
  140. regulator-name = "2P5V";
  141. regulator-min-microvolt = <2500000>;
  142. regulator-max-microvolt = <2500000>;
  143. regulator-always-on;
  144. };
  145. reg_usb_h1_vbus: regulator-usb-h1-vbus {
  146. compatible = "regulator-fixed";
  147. regulator-name = "usb_h1_vbus";
  148. regulator-min-microvolt = <5000000>;
  149. regulator-max-microvolt = <5000000>;
  150. gpio = <&gpio3 30 0>;
  151. enable-active-high;
  152. };
  153. reg_usb_otg_vbus: regulator-usb-otg-vbus {
  154. compatible = "regulator-fixed";
  155. regulator-name = "usb_otg_vbus";
  156. regulator-min-microvolt = <5000000>;
  157. regulator-max-microvolt = <5000000>;
  158. gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
  159. enable-active-high;
  160. };
  161. reg_12p0: regulator-12p0v {
  162. compatible = "regulator-fixed";
  163. regulator-name = "12P0V";
  164. regulator-min-microvolt = <12000000>;
  165. regulator-max-microvolt = <12000000>;
  166. gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
  167. enable-active-high;
  168. };
  169. sound {
  170. compatible = "fsl,imx-audio-tlv320";
  171. model = "imx-tlv320";
  172. ssi-controller = <&ssi1>;
  173. audio-codec = <&tlv320aic3105>;
  174. /* routing of sink, source */
  175. audio-routing =
  176. /* TLV320 LINE1L pin <-> Mic Jack connector */
  177. "LINE1L", "Mic Jack",
  178. /* board Headphone Jack <-> HPOUT */
  179. "Headphone Jack", "HPLOUT",
  180. "Headphone Jack", "HPROUT",
  181. "Mic Jack", "Mic Bias";
  182. mux-int-port = <1>;
  183. mux-ext-port = <6>;
  184. };
  185. };
  186. &audmux {
  187. pinctrl-names = "default";
  188. pinctrl-0 = <&pinctrl_audmux>;
  189. status = "okay";
  190. };
  191. &clks {
  192. assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
  193. <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
  194. assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
  195. <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
  196. };
  197. &fec {
  198. pinctrl-names = "default";
  199. pinctrl-0 = <&pinctrl_enet>;
  200. phy-mode = "rgmii-id";
  201. status = "okay";
  202. };
  203. &i2c1 {
  204. clock-frequency = <100000>;
  205. pinctrl-names = "default";
  206. pinctrl-0 = <&pinctrl_i2c1>;
  207. status = "okay";
  208. gsc: gsc@20 {
  209. compatible = "gw,gsc";
  210. reg = <0x20>;
  211. interrupt-parent = <&gpio1>;
  212. interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
  213. interrupt-controller;
  214. #interrupt-cells = <1>;
  215. #size-cells = <0>;
  216. adc {
  217. compatible = "gw,gsc-adc";
  218. #address-cells = <1>;
  219. #size-cells = <0>;
  220. channel@0 {
  221. gw,mode = <0>;
  222. reg = <0x00>;
  223. label = "temp";
  224. };
  225. channel@2 {
  226. gw,mode = <1>;
  227. reg = <0x02>;
  228. label = "vdd_vin";
  229. };
  230. channel@5 {
  231. gw,mode = <1>;
  232. reg = <0x05>;
  233. label = "vdd_3p3";
  234. };
  235. channel@8 {
  236. gw,mode = <1>;
  237. reg = <0x08>;
  238. label = "vdd_bat";
  239. };
  240. channel@b {
  241. gw,mode = <1>;
  242. reg = <0x0b>;
  243. label = "vdd_5p0";
  244. };
  245. channel@e {
  246. gw,mode = <1>;
  247. reg = <0xe>;
  248. label = "vdd_arm";
  249. };
  250. channel@11 {
  251. gw,mode = <1>;
  252. reg = <0x11>;
  253. label = "vdd_soc";
  254. };
  255. channel@14 {
  256. gw,mode = <1>;
  257. reg = <0x14>;
  258. label = "vdd_3p0";
  259. };
  260. channel@17 {
  261. gw,mode = <1>;
  262. reg = <0x17>;
  263. label = "vdd_1p5";
  264. };
  265. channel@1d {
  266. gw,mode = <1>;
  267. reg = <0x1d>;
  268. label = "vdd_1p8";
  269. };
  270. channel@20 {
  271. gw,mode = <1>;
  272. reg = <0x20>;
  273. label = "vdd_an1";
  274. };
  275. channel@23 {
  276. gw,mode = <1>;
  277. reg = <0x23>;
  278. label = "vdd_2p5";
  279. };
  280. };
  281. };
  282. gsc_gpio: gpio@23 {
  283. compatible = "nxp,pca9555";
  284. reg = <0x23>;
  285. gpio-controller;
  286. #gpio-cells = <2>;
  287. interrupt-parent = <&gsc>;
  288. interrupts = <4>;
  289. };
  290. eeprom1: eeprom@50 {
  291. compatible = "atmel,24c02";
  292. reg = <0x50>;
  293. pagesize = <16>;
  294. };
  295. eeprom2: eeprom@51 {
  296. compatible = "atmel,24c02";
  297. reg = <0x51>;
  298. pagesize = <16>;
  299. };
  300. eeprom3: eeprom@52 {
  301. compatible = "atmel,24c02";
  302. reg = <0x52>;
  303. pagesize = <16>;
  304. };
  305. eeprom4: eeprom@53 {
  306. compatible = "atmel,24c02";
  307. reg = <0x53>;
  308. pagesize = <16>;
  309. };
  310. dts1672: rtc@68 {
  311. compatible = "dallas,ds1672";
  312. reg = <0x68>;
  313. };
  314. };
  315. &i2c2 {
  316. clock-frequency = <400000>;
  317. pinctrl-names = "default";
  318. pinctrl-0 = <&pinctrl_i2c2>;
  319. status = "okay";
  320. ltc3676: pmic@3c {
  321. compatible = "lltc,ltc3676";
  322. reg = <0x3c>;
  323. interrupt-parent = <&gpio1>;
  324. interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
  325. regulators {
  326. /* VDD_1P8 (1+R1/R2 = 2.505): Aud/eMMC/microSD/Touch */
  327. reg_1p8v: sw1 {
  328. regulator-name = "vdd1p8";
  329. regulator-min-microvolt = <1033310>;
  330. regulator-max-microvolt = <2004000>;
  331. lltc,fb-voltage-divider = <301000 200000>;
  332. regulator-ramp-delay = <7000>;
  333. regulator-boot-on;
  334. regulator-always-on;
  335. };
  336. /* VDD_DDR (1+R1/R2 = 2.105) */
  337. reg_vdd_ddr: sw2 {
  338. regulator-name = "vddddr";
  339. regulator-min-microvolt = <868310>;
  340. regulator-max-microvolt = <1684000>;
  341. lltc,fb-voltage-divider = <221000 200000>;
  342. regulator-ramp-delay = <7000>;
  343. regulator-boot-on;
  344. regulator-always-on;
  345. };
  346. /* VDD_ARM (1+R1/R2 = 1.635) */
  347. reg_vdd_arm: sw3 {
  348. regulator-name = "vddarm";
  349. regulator-min-microvolt = <674400>;
  350. regulator-max-microvolt = <1308000>;
  351. lltc,fb-voltage-divider = <127000 200000>;
  352. regulator-ramp-delay = <7000>;
  353. regulator-boot-on;
  354. regulator-always-on;
  355. linux,phandle = <&reg_vdd_arm>;
  356. };
  357. /* VDD_SOC (1+R1/R2 = 1.635) */
  358. reg_vdd_soc: sw4 {
  359. regulator-name = "vddsoc";
  360. regulator-min-microvolt = <674400>;
  361. regulator-max-microvolt = <1308000>;
  362. lltc,fb-voltage-divider = <127000 200000>;
  363. regulator-ramp-delay = <7000>;
  364. regulator-boot-on;
  365. regulator-always-on;
  366. linux,phandle = <&reg_vdd_soc>;
  367. };
  368. /* VDD_1P0 (1+R1/R2 = 1.38): */
  369. reg_1p0v: ldo2 {
  370. regulator-name = "vdd1p0";
  371. regulator-min-microvolt = <1002777>;
  372. regulator-max-microvolt = <1002777>;
  373. lltc,fb-voltage-divider = <100000 261000>;
  374. regulator-boot-on;
  375. regulator-always-on;
  376. };
  377. /* VDD_HIGH (1+R1/R2 = 4.17) */
  378. reg_3p0v: ldo4 {
  379. regulator-name = "vdd3p0";
  380. regulator-min-microvolt = <3023250>;
  381. regulator-max-microvolt = <3023250>;
  382. lltc,fb-voltage-divider = <634000 200000>;
  383. regulator-boot-on;
  384. regulator-always-on;
  385. };
  386. };
  387. };
  388. };
  389. &i2c3 {
  390. clock-frequency = <400000>;
  391. pinctrl-names = "default";
  392. pinctrl-0 = <&pinctrl_i2c3>;
  393. status = "okay";
  394. tlv320aic3105: codec@18 {
  395. compatible = "ti,tlv320aic3x";
  396. reg = <0x18>;
  397. reset-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
  398. clocks = <&clks IMX6QDL_CLK_CKO>;
  399. ai3x-micbias-vg = <2>; /* MICBIAS_2_5V */
  400. /* Regulators */
  401. DRVDD-supply = <&reg_3p3v>;
  402. AVDD-supply = <&reg_3p3v>;
  403. IOVDD-supply = <&reg_3p3v>;
  404. DVDD-supply = <&reg_1p8v>;
  405. };
  406. accelerometer@1d {
  407. compatible = "fsl,mma8451";
  408. reg = <0x1d>;
  409. interrupt-parent = <&gpio7>;
  410. interrupts = <11 IRQ_TYPE_EDGE_RISING>;
  411. interrupt-names = "INT2";
  412. };
  413. /* headphone detect */
  414. ts3a227e@3b {
  415. compatible = "ti,ts3a227e";
  416. reg = <0x3b>;
  417. interrupt-parent = <&gpio5>;
  418. interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
  419. ti,micbias = <4>; /* 2.5V micbias */
  420. };
  421. };
  422. &ldb {
  423. status = "okay";
  424. lvds-channel@0 {
  425. fsl,data-mapping = "spwg";
  426. fsl,data-width = <18>;
  427. status = "okay";
  428. display-timings {
  429. native-mode = <&timing0>;
  430. timing0: g101evn010 {
  431. clock-frequency = <68930000>;
  432. hactive = <1280>;
  433. vactive = <800>;
  434. hback-porch = <220>;
  435. hfront-porch = <40>;
  436. vback-porch = <21>;
  437. vfront-porch = <7>;
  438. hsync-len = <60>;
  439. vsync-len = <10>;
  440. };
  441. };
  442. };
  443. };
  444. &pwm1 {
  445. #pwm-cells = <2>;
  446. pinctrl-names = "default";
  447. pinctrl-0 = <&pinctrl_pwm1>;
  448. status = "okay";
  449. };
  450. &ssi1 {
  451. status = "okay";
  452. };
  453. &uart1 {
  454. pinctrl-names = "default";
  455. pinctrl-0 = <&pinctrl_uart1>;
  456. status = "okay";
  457. };
  458. &uart2 {
  459. pinctrl-names = "default";
  460. pinctrl-0 = <&pinctrl_uart2>;
  461. status = "okay";
  462. };
  463. &usbotg {
  464. vbus-supply = <&reg_usb_otg_vbus>;
  465. pinctrl-names = "default";
  466. pinctrl-0 = <&pinctrl_usbotg>;
  467. disable-over-current;
  468. status = "okay";
  469. };
  470. &usbh1 {
  471. vbus-supply = <&reg_usb_h1_vbus>;
  472. status = "okay";
  473. };
  474. &usdhc1 {
  475. pinctrl-names = "default";
  476. pinctrl-0 = <&pinctrl_usdhc1_200mhz>;
  477. vmmc-supply = <&reg_3p3v>;
  478. non-removable;
  479. bus-width = <4>;
  480. status = "okay";
  481. };
  482. &usdhc2 {
  483. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  484. pinctrl-0 = <&pinctrl_usdhc2>;
  485. pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
  486. pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
  487. cd-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
  488. vmmc-supply = <&reg_3p3v>;
  489. max-frequency = <100000000>;
  490. status = "okay";
  491. };
  492. &usdhc3 {
  493. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  494. pinctrl-0 = <&pinctrl_usdhc3>;
  495. pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
  496. pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
  497. non-removable;
  498. vmmc-supply = <&reg_3p3v>;
  499. keep-power-in-suspend;
  500. status = "okay";
  501. };
  502. &wdog1 {
  503. pinctrl-names = "default";
  504. pinctrl-0 = <&pinctrl_wdog>;
  505. fsl,ext-reset-output;
  506. };
  507. &iomuxc {
  508. pinctrl_audmux: audmuxgrp {
  509. fsl,pins = <
  510. MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x130b0
  511. MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x130b0
  512. MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x130b0
  513. MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x130b0
  514. MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* MCK */
  515. >;
  516. };
  517. pinctrl_enet: enetgrp {
  518. fsl,pins = <
  519. MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
  520. MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
  521. MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
  522. MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
  523. MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
  524. MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
  525. MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
  526. MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
  527. MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
  528. MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
  529. MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
  530. MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
  531. MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
  532. MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
  533. MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
  534. MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x4001b0b0 /* PHY_RST# */
  535. MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x4001b0b0 /* PHY_EN */
  536. >;
  537. };
  538. pinctrl_gpio_leds: gpioledsgrp {
  539. fsl,pins = <
  540. MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0
  541. >;
  542. };
  543. pinctrl_i2c1: i2c1grp {
  544. fsl,pins = <
  545. MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
  546. MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
  547. MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 /* GSC_IRQ# */
  548. >;
  549. };
  550. pinctrl_i2c2: i2c2grp {
  551. fsl,pins = <
  552. MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
  553. MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  554. MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
  555. >;
  556. };
  557. pinctrl_i2c3: i2c3grp {
  558. fsl,pins = <
  559. /* I2C3 */
  560. MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
  561. MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
  562. /* Headphone Detect */
  563. MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x0001b0b0 /* HPDET_IRQ# */
  564. MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x0001b0b0 /* HPDET_MIC# */
  565. /* Codec */
  566. MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x0001b0b0 /* CODEC_RST# */
  567. /* Touch Controller */
  568. MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b0b0 /* TOUCH_IRQ# */
  569. MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x0001b0b0 /* TOUCH_RST */
  570. /* Stow Sensor */
  571. MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x0001b0b0 /* ACCEL_IRQ2 */
  572. MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x0001b0b0 /* ACCEL_IRQ1 */
  573. >;
  574. };
  575. pinctrl_pwm1: pwm1grp {
  576. fsl,pins = <
  577. MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
  578. >;
  579. };
  580. pinctrl_uart1: uart1grp {
  581. fsl,pins = <
  582. MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
  583. MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
  584. MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x1b0b1 /* TXEN */
  585. >;
  586. };
  587. pinctrl_uart2: uart2grp {
  588. fsl,pins = <
  589. MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
  590. MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
  591. >;
  592. };
  593. pinctrl_usbotg: usbotggrp {
  594. fsl,pins = <
  595. MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059
  596. MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x4001b0b0 /* PWR_EN */
  597. MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */
  598. >;
  599. };
  600. pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
  601. fsl,pins = <
  602. MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x4001b0b0 /* EMMY_EN */
  603. MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x4001b0b0 /* EMMY_CFG1# */
  604. MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x4001b0b0 /* EMMY_CFG2# */
  605. MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x0001b0b0 /* EMMY_BTWAKE# */
  606. MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x0001b0b0 /* EMMY_WFWAKE# */
  607. MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9
  608. MX6QDL_PAD_SD1_CMD__SD1_CMD 0x100f9
  609. MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
  610. MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
  611. MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
  612. MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
  613. >;
  614. };
  615. pinctrl_usdhc2: usdhc2grp {
  616. fsl,pins = <
  617. MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
  618. MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
  619. MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
  620. MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
  621. MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
  622. MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
  623. MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x17059 /* CD */
  624. MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x17059
  625. >;
  626. };
  627. pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
  628. fsl,pins = <
  629. MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9
  630. MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9
  631. MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
  632. MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
  633. MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
  634. MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
  635. MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x170b9 /* CD */
  636. MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x170b9
  637. >;
  638. };
  639. pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
  640. fsl,pins = <
  641. MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9
  642. MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9
  643. MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
  644. MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
  645. MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
  646. MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
  647. MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x170f9 /* CD */
  648. MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x170f9
  649. >;
  650. };
  651. pinctrl_usdhc3: usdhc3grp {
  652. fsl,pins = <
  653. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
  654. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
  655. MX6QDL_PAD_SD3_RST__SD3_RESET 0x10059
  656. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
  657. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
  658. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
  659. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
  660. MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
  661. MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
  662. MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
  663. MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
  664. >;
  665. };
  666. pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
  667. fsl,pins = <
  668. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
  669. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
  670. MX6QDL_PAD_SD3_RST__SD3_RESET 0x100b9
  671. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
  672. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
  673. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
  674. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
  675. MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
  676. MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
  677. MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
  678. MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
  679. >;
  680. };
  681. pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
  682. fsl,pins = <
  683. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
  684. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
  685. MX6QDL_PAD_SD3_RST__SD3_RESET 0x100f9
  686. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
  687. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
  688. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
  689. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
  690. MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
  691. MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
  692. MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
  693. MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
  694. >;
  695. };
  696. pinctrl_wdog: wdoggrp {
  697. fsl,pins = <
  698. MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
  699. >;
  700. };
  701. };