imx6qdl-gw560x.dtsi 21 KB

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  1. /*
  2. * Copyright 2017 Gateworks Corporation
  3. *
  4. * This file is dual-licensed: you can use it either under the terms
  5. * of the GPL or the X11 license, at your option. Note that this dual
  6. * licensing only applies to this file, and not this project as a
  7. * whole.
  8. *
  9. * a) This file is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of
  12. * the License, or (at your option) any later version.
  13. *
  14. * This file is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public
  20. * License along with this file; if not, write to the Free
  21. * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  22. * MA 02110-1301 USA
  23. *
  24. * Or, alternatively,
  25. *
  26. * b) Permission is hereby granted, free of charge, to any person
  27. * obtaining a copy of this software and associated documentation
  28. * files (the "Software"), to deal in the Software without
  29. * restriction, including without limitation the rights to use,
  30. * copy, modify, merge, publish, distribute, sublicense, and/or
  31. * sell copies of the Software, and to permit persons to whom the
  32. * Software is furnished to do so, subject to the following
  33. * conditions:
  34. *
  35. * The above copyright notice and this permission notice shall be
  36. * included in all copies or substantial portions of the Software.
  37. *
  38. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40. * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42. * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  43. * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45. * OTHER DEALINGS IN THE SOFTWARE.
  46. */
  47. #include <dt-bindings/gpio/gpio.h>
  48. #include <dt-bindings/input/input.h>
  49. #include <dt-bindings/interrupt-controller/irq.h>
  50. / {
  51. /* these are used by bootloader for disabling nodes */
  52. aliases {
  53. led0 = &led0;
  54. led1 = &led1;
  55. led2 = &led2;
  56. ssi0 = &ssi1;
  57. usb0 = &usbh1;
  58. usb1 = &usbotg;
  59. };
  60. chosen {
  61. stdout-path = &uart2;
  62. };
  63. backlight-display {
  64. compatible = "pwm-backlight";
  65. pwms = <&pwm4 0 5000000>;
  66. brightness-levels = <
  67. 0 1 2 3 4 5 6 7 8 9
  68. 10 11 12 13 14 15 16 17 18 19
  69. 20 21 22 23 24 25 26 27 28 29
  70. 30 31 32 33 34 35 36 37 38 39
  71. 40 41 42 43 44 45 46 47 48 49
  72. 50 51 52 53 54 55 56 57 58 59
  73. 60 61 62 63 64 65 66 67 68 69
  74. 70 71 72 73 74 75 76 77 78 79
  75. 80 81 82 83 84 85 86 87 88 89
  76. 90 91 92 93 94 95 96 97 98 99
  77. 100
  78. >;
  79. default-brightness-level = <100>;
  80. };
  81. backlight-keypad {
  82. compatible = "gpio-backlight";
  83. gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
  84. default-on;
  85. };
  86. gpio-keys {
  87. compatible = "gpio-keys";
  88. user-pb {
  89. label = "user_pb";
  90. gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
  91. linux,code = <BTN_0>;
  92. };
  93. user-pb1x {
  94. label = "user_pb1x";
  95. linux,code = <BTN_1>;
  96. interrupt-parent = <&gsc>;
  97. interrupts = <0>;
  98. };
  99. key-erased {
  100. label = "key-erased";
  101. linux,code = <BTN_2>;
  102. interrupt-parent = <&gsc>;
  103. interrupts = <1>;
  104. };
  105. eeprom-wp {
  106. label = "eeprom_wp";
  107. linux,code = <BTN_3>;
  108. interrupt-parent = <&gsc>;
  109. interrupts = <2>;
  110. };
  111. tamper {
  112. label = "tamper";
  113. linux,code = <BTN_4>;
  114. interrupt-parent = <&gsc>;
  115. interrupts = <5>;
  116. };
  117. switch-hold {
  118. label = "switch_hold";
  119. linux,code = <BTN_5>;
  120. interrupt-parent = <&gsc>;
  121. interrupts = <7>;
  122. };
  123. };
  124. leds {
  125. compatible = "gpio-leds";
  126. pinctrl-names = "default";
  127. pinctrl-0 = <&pinctrl_gpio_leds>;
  128. led0: led-user1 {
  129. label = "user1";
  130. gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
  131. default-state = "on";
  132. linux,default-trigger = "heartbeat";
  133. };
  134. led1: led-user2 {
  135. label = "user2";
  136. gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
  137. default-state = "off";
  138. };
  139. led2: led-user3 {
  140. label = "user3";
  141. gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
  142. default-state = "off";
  143. };
  144. };
  145. memory@10000000 {
  146. device_type = "memory";
  147. reg = <0x10000000 0x40000000>;
  148. };
  149. pps {
  150. compatible = "pps-gpio";
  151. pinctrl-names = "default";
  152. pinctrl-0 = <&pinctrl_pps>;
  153. gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
  154. };
  155. reg_2p5v: regulator-2p5v {
  156. compatible = "regulator-fixed";
  157. regulator-name = "2P5V";
  158. regulator-min-microvolt = <2500000>;
  159. regulator-max-microvolt = <2500000>;
  160. regulator-always-on;
  161. };
  162. reg_3p3v: regulator-3p3v {
  163. compatible = "regulator-fixed";
  164. regulator-name = "3P3V";
  165. regulator-min-microvolt = <3300000>;
  166. regulator-max-microvolt = <3300000>;
  167. regulator-always-on;
  168. };
  169. reg_5p0v: regulator-5p0v {
  170. compatible = "regulator-fixed";
  171. regulator-name = "5P0V";
  172. regulator-min-microvolt = <5000000>;
  173. regulator-max-microvolt = <5000000>;
  174. regulator-always-on;
  175. };
  176. reg_12p0v: regulator-12p0v {
  177. compatible = "regulator-fixed";
  178. regulator-name = "12P0V";
  179. regulator-min-microvolt = <12000000>;
  180. regulator-max-microvolt = <12000000>;
  181. gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
  182. enable-active-high;
  183. };
  184. reg_1p4v: regulator-vddsoc {
  185. compatible = "regulator-fixed";
  186. regulator-name = "vdd_soc";
  187. regulator-min-microvolt = <1400000>;
  188. regulator-max-microvolt = <1400000>;
  189. regulator-always-on;
  190. };
  191. reg_usb_h1_vbus: regulator-usb-h1-vbus {
  192. compatible = "regulator-fixed";
  193. regulator-name = "usb_h1_vbus";
  194. regulator-min-microvolt = <5000000>;
  195. regulator-max-microvolt = <5000000>;
  196. regulator-always-on;
  197. };
  198. reg_usb_otg_vbus: regulator-usb-otg-vbus {
  199. compatible = "regulator-fixed";
  200. regulator-name = "usb_otg_vbus";
  201. regulator-min-microvolt = <5000000>;
  202. regulator-max-microvolt = <5000000>;
  203. gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
  204. enable-active-high;
  205. };
  206. sound {
  207. compatible = "fsl,imx6q-ventana-sgtl5000",
  208. "fsl,imx-audio-sgtl5000";
  209. model = "sgtl5000-audio";
  210. ssi-controller = <&ssi1>;
  211. audio-codec = <&sgtl5000>;
  212. audio-routing =
  213. "MIC_IN", "Mic Jack",
  214. "Mic Jack", "Mic Bias",
  215. "Headphone Jack", "HP_OUT";
  216. mux-int-port = <1>;
  217. mux-ext-port = <4>;
  218. };
  219. };
  220. &audmux {
  221. pinctrl-names = "default";
  222. pinctrl-0 = <&pinctrl_audmux>;
  223. status = "okay";
  224. };
  225. &ecspi3 {
  226. cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
  227. pinctrl-names = "default";
  228. pinctrl-0 = <&pinctrl_ecspi3>;
  229. status = "okay";
  230. };
  231. &can1 {
  232. pinctrl-names = "default";
  233. pinctrl-0 = <&pinctrl_flexcan>;
  234. status = "okay";
  235. };
  236. &clks {
  237. assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
  238. <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
  239. assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
  240. <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
  241. };
  242. &fec {
  243. pinctrl-names = "default";
  244. pinctrl-0 = <&pinctrl_enet>;
  245. phy-mode = "rgmii-id";
  246. phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
  247. status = "okay";
  248. };
  249. &hdmi {
  250. ddc-i2c-bus = <&i2c3>;
  251. status = "okay";
  252. };
  253. &i2c1 {
  254. clock-frequency = <100000>;
  255. pinctrl-names = "default";
  256. pinctrl-0 = <&pinctrl_i2c1>;
  257. status = "okay";
  258. gsc: gsc@20 {
  259. compatible = "gw,gsc";
  260. reg = <0x20>;
  261. interrupt-parent = <&gpio1>;
  262. interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
  263. interrupt-controller;
  264. #interrupt-cells = <1>;
  265. #size-cells = <0>;
  266. adc {
  267. compatible = "gw,gsc-adc";
  268. #address-cells = <1>;
  269. #size-cells = <0>;
  270. channel@0 {
  271. gw,mode = <0>;
  272. reg = <0x00>;
  273. label = "temp";
  274. };
  275. channel@2 {
  276. gw,mode = <1>;
  277. reg = <0x02>;
  278. label = "vdd_vin";
  279. };
  280. channel@5 {
  281. gw,mode = <1>;
  282. reg = <0x05>;
  283. label = "vdd_3p3";
  284. };
  285. channel@8 {
  286. gw,mode = <1>;
  287. reg = <0x08>;
  288. label = "vdd_bat";
  289. };
  290. channel@b {
  291. gw,mode = <1>;
  292. reg = <0x0b>;
  293. label = "vdd_5p0";
  294. };
  295. channel@e {
  296. gw,mode = <1>;
  297. reg = <0xe>;
  298. label = "vdd_arm";
  299. };
  300. channel@11 {
  301. gw,mode = <1>;
  302. reg = <0x11>;
  303. label = "vdd_soc";
  304. };
  305. channel@14 {
  306. gw,mode = <1>;
  307. reg = <0x14>;
  308. label = "vdd_3p0";
  309. };
  310. channel@17 {
  311. gw,mode = <1>;
  312. reg = <0x17>;
  313. label = "vdd_1p5";
  314. };
  315. channel@1d {
  316. gw,mode = <1>;
  317. reg = <0x1d>;
  318. label = "vdd_1p8";
  319. };
  320. channel@20 {
  321. gw,mode = <1>;
  322. reg = <0x20>;
  323. label = "vdd_an1";
  324. };
  325. channel@23 {
  326. gw,mode = <1>;
  327. reg = <0x23>;
  328. label = "vdd_2p5";
  329. };
  330. channel@26 {
  331. gw,mode = <1>;
  332. reg = <0x26>;
  333. label = "vdd_gps";
  334. };
  335. channel@29 {
  336. gw,mode = <1>;
  337. reg = <0x29>;
  338. label = "vdd_an2";
  339. };
  340. };
  341. };
  342. gsc_gpio: gpio@23 {
  343. compatible = "nxp,pca9555";
  344. reg = <0x23>;
  345. gpio-controller;
  346. #gpio-cells = <2>;
  347. interrupt-parent = <&gsc>;
  348. interrupts = <4>;
  349. };
  350. eeprom1: eeprom@50 {
  351. compatible = "atmel,24c02";
  352. reg = <0x50>;
  353. pagesize = <16>;
  354. };
  355. eeprom2: eeprom@51 {
  356. compatible = "atmel,24c02";
  357. reg = <0x51>;
  358. pagesize = <16>;
  359. };
  360. eeprom3: eeprom@52 {
  361. compatible = "atmel,24c02";
  362. reg = <0x52>;
  363. pagesize = <16>;
  364. };
  365. eeprom4: eeprom@53 {
  366. compatible = "atmel,24c02";
  367. reg = <0x53>;
  368. pagesize = <16>;
  369. };
  370. ds1672: rtc@68 {
  371. compatible = "dallas,ds1672";
  372. reg = <0x68>;
  373. };
  374. };
  375. &i2c2 {
  376. clock-frequency = <100000>;
  377. pinctrl-names = "default";
  378. pinctrl-0 = <&pinctrl_i2c2>;
  379. status = "okay";
  380. sgtl5000: codec@a {
  381. compatible = "fsl,sgtl5000";
  382. reg = <0x0a>;
  383. #sound-dai-cells = <0>;
  384. clocks = <&clks IMX6QDL_CLK_CKO>;
  385. VDDA-supply = <&reg_1p8v>;
  386. VDDIO-supply = <&reg_3p3v>;
  387. };
  388. magn@1c {
  389. compatible = "st,lsm9ds1-magn";
  390. reg = <0x1c>;
  391. pinctrl-names = "default";
  392. pinctrl-0 = <&pinctrl_mag>;
  393. interrupt-parent = <&gpio5>;
  394. interrupts = <9 IRQ_TYPE_EDGE_RISING>;
  395. };
  396. tca8418: keypad@34 {
  397. compatible = "ti,tca8418";
  398. pinctrl-names = "default";
  399. pinctrl-0 = <&pinctrl_keypad>;
  400. reg = <0x34>;
  401. interrupt-parent = <&gpio5>;
  402. interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
  403. linux,keymap = < MATRIX_KEY(0x00, 0x01, BTN_0)
  404. MATRIX_KEY(0x00, 0x00, BTN_1)
  405. MATRIX_KEY(0x01, 0x01, BTN_2)
  406. MATRIX_KEY(0x01, 0x00, BTN_3)
  407. MATRIX_KEY(0x02, 0x00, BTN_4)
  408. MATRIX_KEY(0x00, 0x03, BTN_5)
  409. MATRIX_KEY(0x00, 0x02, BTN_6)
  410. MATRIX_KEY(0x01, 0x03, BTN_7)
  411. MATRIX_KEY(0x01, 0x02, BTN_8)
  412. MATRIX_KEY(0x02, 0x02, BTN_9)
  413. >;
  414. keypad,num-rows = <4>;
  415. keypad,num-columns = <4>;
  416. };
  417. ltc3676: pmic@3c {
  418. compatible = "lltc,ltc3676";
  419. pinctrl-names = "default";
  420. pinctrl-0 = <&pinctrl_pmic>;
  421. reg = <0x3c>;
  422. interrupt-parent = <&gpio1>;
  423. interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
  424. regulators {
  425. /* VDD_DDR (1+R1/R2 = 2.105) */
  426. reg_vdd_ddr: sw2 {
  427. regulator-name = "vddddr";
  428. regulator-min-microvolt = <868310>;
  429. regulator-max-microvolt = <1684000>;
  430. lltc,fb-voltage-divider = <221000 200000>;
  431. regulator-ramp-delay = <7000>;
  432. regulator-boot-on;
  433. regulator-always-on;
  434. };
  435. /* VDD_ARM (1+R1/R2 = 1.931) */
  436. reg_vdd_arm: sw3 {
  437. regulator-name = "vddarm";
  438. regulator-min-microvolt = <796551>;
  439. regulator-max-microvolt = <1544827>;
  440. lltc,fb-voltage-divider = <243000 261000>;
  441. regulator-ramp-delay = <7000>;
  442. regulator-boot-on;
  443. regulator-always-on;
  444. linux,phandle = <&reg_vdd_arm>;
  445. };
  446. /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
  447. reg_1p8v: sw4 {
  448. regulator-name = "vdd1p8";
  449. regulator-min-microvolt = <1033310>;
  450. regulator-max-microvolt = <2004000>;
  451. lltc,fb-voltage-divider = <301000 200000>;
  452. regulator-ramp-delay = <7000>;
  453. regulator-boot-on;
  454. regulator-always-on;
  455. };
  456. /* VDD_1P0 (1+R1/R2 = 1.39): PCIe/ENET-PHY */
  457. reg_1p0v: ldo2 {
  458. regulator-name = "vdd1p0";
  459. regulator-min-microvolt = <950000>;
  460. regulator-max-microvolt = <1050000>;
  461. lltc,fb-voltage-divider = <78700 200000>;
  462. regulator-boot-on;
  463. regulator-always-on;
  464. };
  465. /* VDD_AUD_1P8: Audio codec */
  466. reg_aud_1p8v: ldo3 {
  467. regulator-name = "vdd1p8a";
  468. regulator-min-microvolt = <1800000>;
  469. regulator-max-microvolt = <1800000>;
  470. regulator-boot-on;
  471. };
  472. /* VDD_HIGH (1+R1/R2 = 4.17) */
  473. reg_3p0v: ldo4 {
  474. regulator-name = "vdd3p0";
  475. regulator-min-microvolt = <3023250>;
  476. regulator-max-microvolt = <3023250>;
  477. lltc,fb-voltage-divider = <634000 200000>;
  478. regulator-boot-on;
  479. regulator-always-on;
  480. };
  481. };
  482. };
  483. imu@6a {
  484. compatible = "st,lsm9ds1-imu";
  485. reg = <0x6a>;
  486. st,drdy-int-pin = <1>;
  487. pinctrl-names = "default";
  488. pinctrl-0 = <&pinctrl_imu>;
  489. interrupt-parent = <&gpio5>;
  490. interrupts = <6 IRQ_TYPE_LEVEL_HIGH>;
  491. };
  492. };
  493. &i2c3 {
  494. clock-frequency = <100000>;
  495. pinctrl-names = "default";
  496. pinctrl-0 = <&pinctrl_i2c3>;
  497. status = "okay";
  498. egalax_ts: touchscreen@4 {
  499. compatible = "eeti,egalax_ts";
  500. reg = <0x04>;
  501. interrupt-parent = <&gpio5>;
  502. interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
  503. wakeup-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
  504. };
  505. };
  506. &ldb {
  507. fsl,dual-channel;
  508. status = "okay";
  509. lvds-channel@0 {
  510. fsl,data-mapping = "spwg";
  511. fsl,data-width = <18>;
  512. status = "okay";
  513. display-timings {
  514. native-mode = <&timing0>;
  515. timing0: hsd100pxn1 {
  516. clock-frequency = <65000000>;
  517. hactive = <1024>;
  518. vactive = <768>;
  519. hback-porch = <220>;
  520. hfront-porch = <40>;
  521. vback-porch = <21>;
  522. vfront-porch = <7>;
  523. hsync-len = <60>;
  524. vsync-len = <10>;
  525. };
  526. };
  527. };
  528. };
  529. &pcie {
  530. pinctrl-names = "default";
  531. pinctrl-0 = <&pinctrl_pcie>;
  532. reset-gpio = <&gpio4 31 GPIO_ACTIVE_LOW>;
  533. status = "okay";
  534. };
  535. &pwm2 {
  536. pinctrl-names = "default";
  537. pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
  538. status = "disabled";
  539. };
  540. &pwm3 {
  541. pinctrl-names = "default";
  542. pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
  543. status = "disabled";
  544. };
  545. &pwm4 {
  546. #pwm-cells = <2>;
  547. pinctrl-names = "default";
  548. pinctrl-0 = <&pinctrl_pwm4>;
  549. status = "okay";
  550. };
  551. &ssi1 {
  552. status = "okay";
  553. };
  554. &uart1 {
  555. pinctrl-names = "default";
  556. pinctrl-0 = <&pinctrl_uart1>;
  557. rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
  558. status = "okay";
  559. };
  560. &uart2 {
  561. pinctrl-names = "default";
  562. pinctrl-0 = <&pinctrl_uart2>;
  563. status = "okay";
  564. };
  565. &uart5 {
  566. pinctrl-names = "default";
  567. pinctrl-0 = <&pinctrl_uart5>;
  568. status = "okay";
  569. };
  570. &usbotg {
  571. vbus-supply = <&reg_usb_otg_vbus>;
  572. pinctrl-names = "default";
  573. pinctrl-0 = <&pinctrl_usbotg>;
  574. disable-over-current;
  575. status = "okay";
  576. };
  577. &usbh1 {
  578. vbus-supply = <&reg_usb_h1_vbus>;
  579. pinctrl-names = "default";
  580. pinctrl-0 = <&pinctrl_usbh1>;
  581. status = "okay";
  582. };
  583. &usdhc2 {
  584. pinctrl-names = "default";
  585. pinctrl-0 = <&pinctrl_usdhc2>;
  586. bus-width = <8>;
  587. vmmc-supply = <&reg_3p3v>;
  588. non-removable;
  589. status = "okay";
  590. };
  591. &usdhc3 {
  592. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  593. pinctrl-0 = <&pinctrl_usdhc3>;
  594. pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
  595. pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
  596. cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
  597. vmmc-supply = <&reg_3p3v>;
  598. status = "okay";
  599. };
  600. &wdog1 {
  601. pinctrl-names = "default";
  602. pinctrl-0 = <&pinctrl_wdog>;
  603. fsl,ext-reset-output;
  604. };
  605. &iomuxc {
  606. pinctrl_audmux: audmuxgrp {
  607. fsl,pins = <
  608. /* AUD4 */
  609. MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
  610. MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0
  611. MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
  612. MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
  613. MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
  614. /* AUD6 */
  615. MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x130b0
  616. MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x130b0
  617. MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x130b0
  618. MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x130b0
  619. >;
  620. };
  621. pinctrl_ecspi3: escpi3grp {
  622. fsl,pins = <
  623. MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
  624. MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
  625. MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
  626. MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1
  627. >;
  628. };
  629. pinctrl_enet: enetgrp {
  630. fsl,pins = <
  631. MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
  632. MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
  633. MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
  634. MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
  635. MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
  636. MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
  637. MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
  638. MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
  639. MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
  640. MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
  641. MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
  642. MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
  643. MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
  644. MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
  645. MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
  646. MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
  647. MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x4001b0b0 /* PHY_RST# */
  648. >;
  649. };
  650. pinctrl_flexcan: flexcangrp {
  651. fsl,pins = <
  652. MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
  653. MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
  654. MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */
  655. >;
  656. };
  657. pinctrl_gpio_leds: gpioledsgrp {
  658. fsl,pins = <
  659. MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
  660. MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
  661. MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
  662. >;
  663. };
  664. pinctrl_i2c1: i2c1grp {
  665. fsl,pins = <
  666. MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
  667. MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
  668. MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
  669. >;
  670. };
  671. pinctrl_i2c2: i2c2grp {
  672. fsl,pins = <
  673. MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
  674. MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  675. >;
  676. };
  677. pinctrl_i2c3: i2c3grp {
  678. fsl,pins = <
  679. MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
  680. MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
  681. MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x4001b0b0 /* DIOI2C_DIS# */
  682. MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x0001b0b0 /* LVDS_TOUCH_IRQ# */
  683. MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x0001b0b0 /* LVDS_BACKEN */
  684. >;
  685. };
  686. pinctrl_imu: imugrp {
  687. fsl,pins = <
  688. MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x1b0b0
  689. >;
  690. };
  691. pinctrl_keypad: keypadgrp {
  692. fsl,pins = <
  693. MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x0001b0b0 /* KEYPAD_IRQ# */
  694. MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x0001b0b0 /* KEYPAD_LED_EN */
  695. >;
  696. };
  697. pinctrl_mag: maggrp {
  698. fsl,pins = <
  699. MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b0
  700. >;
  701. };
  702. pinctrl_pcie: pciegrp {
  703. fsl,pins = <
  704. MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b0 /* PCI_RST# */
  705. MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b0 /* PCIESKT_WDIS# */
  706. >;
  707. };
  708. pinctrl_pmic: pmicgrp {
  709. fsl,pins = <
  710. MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
  711. >;
  712. };
  713. pinctrl_pps: ppsgrp {
  714. fsl,pins = <
  715. MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
  716. >;
  717. };
  718. pinctrl_pwm2: pwm2grp {
  719. fsl,pins = <
  720. MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
  721. >;
  722. };
  723. pinctrl_pwm3: pwm3grp {
  724. fsl,pins = <
  725. MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
  726. >;
  727. };
  728. pinctrl_pwm4: pwm4grp {
  729. fsl,pins = <
  730. MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
  731. >;
  732. };
  733. pinctrl_uart1: uart1grp {
  734. fsl,pins = <
  735. MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
  736. MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
  737. MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */
  738. >;
  739. };
  740. pinctrl_uart2: uart2grp {
  741. fsl,pins = <
  742. MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
  743. MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
  744. >;
  745. };
  746. pinctrl_uart5: uart5grp {
  747. fsl,pins = <
  748. MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
  749. MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
  750. >;
  751. };
  752. pinctrl_usbh1: usbh1grp {
  753. fsl,pins = <
  754. MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* USBHUB_RST# */
  755. >;
  756. };
  757. pinctrl_usbotg: usbotggrp {
  758. fsl,pins = <
  759. MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
  760. MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */
  761. MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */
  762. >;
  763. };
  764. pinctrl_usdhc2: usdhc2grp {
  765. fsl,pins = <
  766. MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9
  767. MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9
  768. MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
  769. MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
  770. MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
  771. MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
  772. MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x170f9
  773. MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x170f9
  774. MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x170f9
  775. MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x170f9
  776. >;
  777. };
  778. pinctrl_usdhc3: usdhc3grp {
  779. fsl,pins = <
  780. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
  781. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
  782. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
  783. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
  784. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
  785. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
  786. MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
  787. MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
  788. >;
  789. };
  790. pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
  791. fsl,pins = <
  792. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
  793. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
  794. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
  795. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
  796. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
  797. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
  798. MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
  799. MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
  800. >;
  801. };
  802. pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
  803. fsl,pins = <
  804. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
  805. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
  806. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
  807. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
  808. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
  809. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
  810. MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
  811. MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
  812. >;
  813. };
  814. pinctrl_wdog: wdoggrp {
  815. fsl,pins = <
  816. MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
  817. >;
  818. };
  819. };