imx6qdl-gw552x.dtsi 9.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright 2014 Gateworks Corporation
  4. */
  5. #include <dt-bindings/gpio/gpio.h>
  6. #include <dt-bindings/input/linux-event-codes.h>
  7. #include <dt-bindings/interrupt-controller/irq.h>
  8. / {
  9. /* these are used by bootloader for disabling nodes */
  10. aliases {
  11. led0 = &led0;
  12. led1 = &led1;
  13. led2 = &led2;
  14. nand = &gpmi;
  15. usb0 = &usbh1;
  16. usb1 = &usbotg;
  17. };
  18. chosen {
  19. bootargs = "console=ttymxc1,115200";
  20. };
  21. gpio-keys {
  22. compatible = "gpio-keys";
  23. user-pb {
  24. label = "user_pb";
  25. gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
  26. linux,code = <BTN_0>;
  27. };
  28. user-pb1x {
  29. label = "user_pb1x";
  30. linux,code = <BTN_1>;
  31. interrupt-parent = <&gsc>;
  32. interrupts = <0>;
  33. };
  34. key-erased {
  35. label = "key-erased";
  36. linux,code = <BTN_2>;
  37. interrupt-parent = <&gsc>;
  38. interrupts = <1>;
  39. };
  40. eeprom-wp {
  41. label = "eeprom_wp";
  42. linux,code = <BTN_3>;
  43. interrupt-parent = <&gsc>;
  44. interrupts = <2>;
  45. };
  46. tamper {
  47. label = "tamper";
  48. linux,code = <BTN_4>;
  49. interrupt-parent = <&gsc>;
  50. interrupts = <5>;
  51. };
  52. switch-hold {
  53. label = "switch_hold";
  54. linux,code = <BTN_5>;
  55. interrupt-parent = <&gsc>;
  56. interrupts = <7>;
  57. };
  58. };
  59. leds {
  60. compatible = "gpio-leds";
  61. pinctrl-names = "default";
  62. pinctrl-0 = <&pinctrl_gpio_leds>;
  63. led0: led-user1 {
  64. label = "user1";
  65. gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
  66. default-state = "on";
  67. linux,default-trigger = "heartbeat";
  68. };
  69. led1: led-user2 {
  70. label = "user2";
  71. gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
  72. default-state = "off";
  73. };
  74. led2: led-user3 {
  75. label = "user3";
  76. gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
  77. default-state = "off";
  78. };
  79. };
  80. memory@10000000 {
  81. device_type = "memory";
  82. reg = <0x10000000 0x20000000>;
  83. };
  84. reg_1p0v: regulator-1p0v {
  85. compatible = "regulator-fixed";
  86. regulator-name = "1P0V";
  87. regulator-min-microvolt = <1000000>;
  88. regulator-max-microvolt = <1000000>;
  89. regulator-always-on;
  90. };
  91. reg_3p3v: regulator-3p3v {
  92. compatible = "regulator-fixed";
  93. regulator-name = "3P3V";
  94. regulator-min-microvolt = <3300000>;
  95. regulator-max-microvolt = <3300000>;
  96. regulator-always-on;
  97. };
  98. reg_5p0v: regulator-5p0v {
  99. compatible = "regulator-fixed";
  100. regulator-name = "5P0V";
  101. regulator-min-microvolt = <5000000>;
  102. regulator-max-microvolt = <5000000>;
  103. regulator-always-on;
  104. };
  105. };
  106. &gpmi {
  107. pinctrl-names = "default";
  108. pinctrl-0 = <&pinctrl_gpmi_nand>;
  109. status = "okay";
  110. };
  111. &hdmi {
  112. ddc-i2c-bus = <&i2c3>;
  113. status = "okay";
  114. };
  115. &i2c1 {
  116. clock-frequency = <100000>;
  117. pinctrl-names = "default";
  118. pinctrl-0 = <&pinctrl_i2c1>;
  119. status = "okay";
  120. gsc: gsc@20 {
  121. compatible = "gw,gsc";
  122. reg = <0x20>;
  123. interrupt-parent = <&gpio1>;
  124. interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
  125. interrupt-controller;
  126. #interrupt-cells = <1>;
  127. #size-cells = <0>;
  128. adc {
  129. compatible = "gw,gsc-adc";
  130. #address-cells = <1>;
  131. #size-cells = <0>;
  132. channel@0 {
  133. gw,mode = <0>;
  134. reg = <0x00>;
  135. label = "temp";
  136. };
  137. channel@2 {
  138. gw,mode = <1>;
  139. reg = <0x02>;
  140. label = "vdd_vin";
  141. };
  142. channel@5 {
  143. gw,mode = <1>;
  144. reg = <0x05>;
  145. label = "vdd_3p3";
  146. };
  147. channel@8 {
  148. gw,mode = <1>;
  149. reg = <0x08>;
  150. label = "vdd_bat";
  151. };
  152. channel@b {
  153. gw,mode = <1>;
  154. reg = <0x0b>;
  155. label = "vdd_5p0";
  156. };
  157. channel@e {
  158. gw,mode = <1>;
  159. reg = <0xe>;
  160. label = "vdd_arm";
  161. };
  162. channel@11 {
  163. gw,mode = <1>;
  164. reg = <0x11>;
  165. label = "vdd_soc";
  166. };
  167. channel@14 {
  168. gw,mode = <1>;
  169. reg = <0x14>;
  170. label = "vdd_3p0";
  171. };
  172. channel@17 {
  173. gw,mode = <1>;
  174. reg = <0x17>;
  175. label = "vdd_1p5";
  176. };
  177. channel@1d {
  178. gw,mode = <1>;
  179. reg = <0x1d>;
  180. label = "vdd_1p8";
  181. };
  182. channel@20 {
  183. gw,mode = <1>;
  184. reg = <0x20>;
  185. label = "vdd_1p0";
  186. };
  187. channel@23 {
  188. gw,mode = <1>;
  189. reg = <0x23>;
  190. label = "vdd_2p5";
  191. };
  192. };
  193. };
  194. gsc_gpio: gpio@23 {
  195. compatible = "nxp,pca9555";
  196. reg = <0x23>;
  197. gpio-controller;
  198. #gpio-cells = <2>;
  199. interrupt-parent = <&gsc>;
  200. interrupts = <4>;
  201. };
  202. eeprom1: eeprom@50 {
  203. compatible = "atmel,24c02";
  204. reg = <0x50>;
  205. pagesize = <16>;
  206. };
  207. eeprom2: eeprom@51 {
  208. compatible = "atmel,24c02";
  209. reg = <0x51>;
  210. pagesize = <16>;
  211. };
  212. eeprom3: eeprom@52 {
  213. compatible = "atmel,24c02";
  214. reg = <0x52>;
  215. pagesize = <16>;
  216. };
  217. eeprom4: eeprom@53 {
  218. compatible = "atmel,24c02";
  219. reg = <0x53>;
  220. pagesize = <16>;
  221. };
  222. rtc: ds1672@68 {
  223. compatible = "dallas,ds1672";
  224. reg = <0x68>;
  225. };
  226. };
  227. &i2c2 {
  228. clock-frequency = <100000>;
  229. pinctrl-names = "default";
  230. pinctrl-0 = <&pinctrl_i2c2>;
  231. status = "okay";
  232. ltc3676: pmic@3c {
  233. compatible = "lltc,ltc3676";
  234. reg = <0x3c>;
  235. pinctrl-names = "default";
  236. pinctrl-0 = <&pinctrl_pmic>;
  237. interrupt-parent = <&gpio1>;
  238. interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
  239. regulators {
  240. /* VDD_SOC (1+R1/R2 = 1.635) */
  241. reg_vdd_soc: sw1 {
  242. regulator-name = "vddsoc";
  243. regulator-min-microvolt = <674400>;
  244. regulator-max-microvolt = <1308000>;
  245. lltc,fb-voltage-divider = <127000 200000>;
  246. regulator-ramp-delay = <7000>;
  247. regulator-boot-on;
  248. regulator-always-on;
  249. };
  250. /* VDD_1P8 (1+R1/R2 = 2.505): ENET-PHY */
  251. reg_1p8v: sw2 {
  252. regulator-name = "vdd1p8";
  253. regulator-min-microvolt = <1033310>;
  254. regulator-max-microvolt = <2004000>;
  255. lltc,fb-voltage-divider = <301000 200000>;
  256. regulator-ramp-delay = <7000>;
  257. regulator-boot-on;
  258. regulator-always-on;
  259. };
  260. /* VDD_ARM (1+R1/R2 = 1.635) */
  261. reg_vdd_arm: sw3 {
  262. regulator-name = "vddarm";
  263. regulator-min-microvolt = <674400>;
  264. regulator-max-microvolt = <1308000>;
  265. lltc,fb-voltage-divider = <127000 200000>;
  266. regulator-ramp-delay = <7000>;
  267. regulator-boot-on;
  268. regulator-always-on;
  269. };
  270. /* VDD_DDR (1+R1/R2 = 2.105) */
  271. reg_vdd_ddr: sw4 {
  272. regulator-name = "vddddr";
  273. regulator-min-microvolt = <868310>;
  274. regulator-max-microvolt = <1684000>;
  275. lltc,fb-voltage-divider = <221000 200000>;
  276. regulator-ramp-delay = <7000>;
  277. regulator-boot-on;
  278. regulator-always-on;
  279. };
  280. /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
  281. reg_2p5v: ldo2 {
  282. regulator-name = "vdd2p5";
  283. regulator-min-microvolt = <2490375>;
  284. regulator-max-microvolt = <2490375>;
  285. lltc,fb-voltage-divider = <487000 200000>;
  286. regulator-boot-on;
  287. regulator-always-on;
  288. };
  289. /* VDD_HIGH (1+R1/R2 = 4.17) */
  290. reg_3p0v: ldo4 {
  291. regulator-name = "vdd3p0";
  292. regulator-min-microvolt = <3023250>;
  293. regulator-max-microvolt = <3023250>;
  294. lltc,fb-voltage-divider = <634000 200000>;
  295. regulator-boot-on;
  296. regulator-always-on;
  297. };
  298. };
  299. };
  300. };
  301. &i2c3 {
  302. clock-frequency = <100000>;
  303. pinctrl-names = "default";
  304. pinctrl-0 = <&pinctrl_i2c3>;
  305. status = "okay";
  306. };
  307. &pcie {
  308. pinctrl-names = "default";
  309. pinctrl-0 = <&pinctrl_pcie>;
  310. reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
  311. status = "okay";
  312. };
  313. &pwm2 {
  314. pinctrl-names = "default";
  315. pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
  316. status = "disabled";
  317. };
  318. &pwm3 {
  319. pinctrl-names = "default";
  320. pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
  321. status = "disabled";
  322. };
  323. &uart2 {
  324. pinctrl-names = "default";
  325. pinctrl-0 = <&pinctrl_uart2>;
  326. status = "okay";
  327. };
  328. &uart3 {
  329. pinctrl-names = "default";
  330. pinctrl-0 = <&pinctrl_uart3>;
  331. status = "okay";
  332. };
  333. &uart5 {
  334. pinctrl-names = "default";
  335. pinctrl-0 = <&pinctrl_uart5>;
  336. status = "okay"; };
  337. &usbh1 {
  338. status = "okay";
  339. };
  340. &usbotg {
  341. vbus-supply = <&reg_5p0v>;
  342. pinctrl-names = "default";
  343. pinctrl-0 = <&pinctrl_usbotg>;
  344. disable-over-current;
  345. status = "okay";
  346. };
  347. &wdog1 {
  348. pinctrl-names = "default";
  349. pinctrl-0 = <&pinctrl_wdog>;
  350. fsl,ext-reset-output;
  351. };
  352. &iomuxc {
  353. pinctrl_gpio_leds: gpioledsgrp {
  354. fsl,pins = <
  355. MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
  356. MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
  357. MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
  358. >;
  359. };
  360. pinctrl_gpmi_nand: gpminandgrp {
  361. fsl,pins = <
  362. MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
  363. MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
  364. MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
  365. MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
  366. MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
  367. MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
  368. MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
  369. MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
  370. MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
  371. MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
  372. MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
  373. MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
  374. MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
  375. MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
  376. MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
  377. >;
  378. };
  379. pinctrl_i2c1: i2c1grp {
  380. fsl,pins = <
  381. MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
  382. MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
  383. MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
  384. >;
  385. };
  386. pinctrl_i2c2: i2c2grp {
  387. fsl,pins = <
  388. MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
  389. MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  390. >;
  391. };
  392. pinctrl_i2c3: i2c3grp {
  393. fsl,pins = <
  394. MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
  395. MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
  396. >;
  397. };
  398. pinctrl_pcie: pciegrp {
  399. fsl,pins = <
  400. MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
  401. >;
  402. };
  403. pinctrl_pmic: pmicgrp {
  404. fsl,pins = <
  405. MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
  406. >;
  407. };
  408. pinctrl_pwm2: pwm2grp {
  409. fsl,pins = <
  410. MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
  411. >;
  412. };
  413. pinctrl_pwm3: pwm3grp {
  414. fsl,pins = <
  415. MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
  416. >;
  417. };
  418. pinctrl_uart2: uart2grp {
  419. fsl,pins = <
  420. MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
  421. MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
  422. >;
  423. };
  424. pinctrl_uart3: uart3grp {
  425. fsl,pins = <
  426. MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
  427. MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
  428. >;
  429. };
  430. pinctrl_uart5: uart5grp {
  431. fsl,pins = <
  432. MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
  433. MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
  434. >;
  435. };
  436. pinctrl_usbotg: usbotggrp {
  437. fsl,pins = <
  438. MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x13059
  439. >;
  440. };
  441. pinctrl_wdog: wdoggrp {
  442. fsl,pins = <
  443. MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
  444. >;
  445. };
  446. };