imx6qdl-ds.dtsi 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. //
  3. // Copyright 2021 Dillon Min <[email protected]>
  4. //
  5. // Based on imx6qdl-sabresd.dtsi which is:
  6. // Copyright 2012 Freescale Semiconductor, Inc.
  7. // Copyright 2011 Linaro Ltd.
  8. #include <dt-bindings/clock/imx6qdl-clock.h>
  9. #include <dt-bindings/gpio/gpio.h>
  10. #include <dt-bindings/input/input.h>
  11. / {
  12. chosen {
  13. stdout-path = &uart4;
  14. };
  15. memory@10000000 {
  16. device_type = "memory";
  17. reg = <0x10000000 0x80000000>;
  18. };
  19. reg_usb_otg_vbus: regulator-usb-otg-vbus {
  20. compatible = "regulator-fixed";
  21. regulator-name = "usb_otg_vbus";
  22. regulator-min-microvolt = <5000000>;
  23. regulator-max-microvolt = <5000000>;
  24. };
  25. reg_usb_h1_vbus: regulator-usb-h1-vbus {
  26. compatible = "regulator-fixed";
  27. regulator-name = "usb_h1_vbus";
  28. regulator-min-microvolt = <5000000>;
  29. regulator-max-microvolt = <5000000>;
  30. };
  31. leds {
  32. compatible = "gpio-leds";
  33. pinctrl-names = "default";
  34. pinctrl-0 = <&pinctrl_gpio_leds>;
  35. led-0 {
  36. gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>;
  37. default-state = "on";
  38. linux,default-trigger = "heartbeat";
  39. };
  40. };
  41. };
  42. &ipu1_csi0_from_ipu1_csi0_mux {
  43. bus-width = <8>;
  44. data-shift = <12>; /* Lines 19:12 used */
  45. hsync-active = <1>;
  46. vsync-active = <1>;
  47. };
  48. &ipu1_csi0_mux_from_parallel_sensor {
  49. remote-endpoint = <&ov2659_to_ipu1_csi0_mux>;
  50. };
  51. &ipu1_csi0 {
  52. pinctrl-names = "default";
  53. pinctrl-0 = <&pinctrl_ipu1_csi0>;
  54. status = "okay";
  55. };
  56. &ecspi1 {
  57. cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
  58. pinctrl-names = "default";
  59. pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_ecspi1_gpio>;
  60. status = "okay";
  61. m25p80: flash@0 {
  62. #address-cells = <1>;
  63. #size-cells = <1>;
  64. compatible = "st,m25p80", "jedec,spi-nor";
  65. spi-max-frequency = <20000000>;
  66. reg = <0>;
  67. };
  68. };
  69. &fec {
  70. pinctrl-names = "default";
  71. pinctrl-0 = <&pinctrl_enet>;
  72. phy-mode = "rgmii-id";
  73. phy-handle = <&phy>;
  74. fsl,magic-packet;
  75. status = "okay";
  76. mdio {
  77. #address-cells = <1>;
  78. #size-cells = <0>;
  79. phy: ethernet-phy@1 {
  80. reg = <1>;
  81. qca,clk-out-frequency = <125000000>;
  82. reset-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
  83. reset-assert-us = <10000>;
  84. };
  85. };
  86. };
  87. &hdmi {
  88. pinctrl-names = "default";
  89. pinctrl-0 = <&pinctrl_hdmi_cec>;
  90. ddc-i2c-bus = <&i2c3>;
  91. status = "okay";
  92. };
  93. &i2c2 {
  94. clock-frequency = <100000>;
  95. pinctrl-names = "default";
  96. pinctrl-0 = <&pinctrl_i2c2>;
  97. status = "okay";
  98. pfuze100: pmic@8 {
  99. compatible = "fsl,pfuze100";
  100. reg = <0x08>;
  101. regulators {
  102. sw1a_reg: sw1ab {
  103. regulator-min-microvolt = <300000>;
  104. regulator-max-microvolt = <1875000>;
  105. regulator-boot-on;
  106. regulator-always-on;
  107. regulator-ramp-delay = <6250>;
  108. };
  109. sw1c_reg: sw1c {
  110. regulator-min-microvolt = <300000>;
  111. regulator-max-microvolt = <1875000>;
  112. regulator-boot-on;
  113. regulator-always-on;
  114. regulator-ramp-delay = <6250>;
  115. };
  116. sw2_reg: sw2 {
  117. regulator-min-microvolt = <800000>;
  118. regulator-max-microvolt = <3300000>;
  119. regulator-boot-on;
  120. regulator-always-on;
  121. regulator-ramp-delay = <6250>;
  122. };
  123. sw3a_reg: sw3a {
  124. regulator-min-microvolt = <400000>;
  125. regulator-max-microvolt = <1975000>;
  126. regulator-boot-on;
  127. regulator-always-on;
  128. };
  129. sw3b_reg: sw3b {
  130. regulator-min-microvolt = <400000>;
  131. regulator-max-microvolt = <1975000>;
  132. regulator-boot-on;
  133. regulator-always-on;
  134. };
  135. sw4_reg: sw4 {
  136. regulator-min-microvolt = <800000>;
  137. regulator-max-microvolt = <3300000>;
  138. regulator-always-on;
  139. };
  140. swbst_reg: swbst {
  141. regulator-min-microvolt = <5000000>;
  142. regulator-max-microvolt = <5150000>;
  143. };
  144. snvs_reg: vsnvs {
  145. regulator-min-microvolt = <1000000>;
  146. regulator-max-microvolt = <3000000>;
  147. regulator-boot-on;
  148. regulator-always-on;
  149. };
  150. vref_reg: vrefddr {
  151. regulator-boot-on;
  152. regulator-always-on;
  153. };
  154. vgen1_reg: vgen1 {
  155. regulator-min-microvolt = <800000>;
  156. regulator-max-microvolt = <1550000>;
  157. };
  158. vgen2_reg: vgen2 {
  159. regulator-min-microvolt = <800000>;
  160. regulator-max-microvolt = <1550000>;
  161. };
  162. vgen3_reg: vgen3 {
  163. regulator-min-microvolt = <1800000>;
  164. regulator-max-microvolt = <3300000>;
  165. };
  166. vgen4_reg: vgen4 {
  167. regulator-min-microvolt = <1800000>;
  168. regulator-max-microvolt = <3300000>;
  169. regulator-always-on;
  170. };
  171. vgen5_reg: vgen5 {
  172. regulator-min-microvolt = <1800000>;
  173. regulator-max-microvolt = <3300000>;
  174. regulator-always-on;
  175. };
  176. vgen6_reg: vgen6 {
  177. regulator-min-microvolt = <1800000>;
  178. regulator-max-microvolt = <3300000>;
  179. regulator-always-on;
  180. };
  181. };
  182. };
  183. };
  184. &i2c3 {
  185. clock-frequency = <100000>;
  186. pinctrl-names = "default";
  187. pinctrl-0 = <&pinctrl_i2c3>;
  188. status = "okay";
  189. ov2659: camera@30 {
  190. compatible = "ovti,ov2659";
  191. pinctrl-names = "default";
  192. pinctrl-0 = <&pinctrl_ov2659>;
  193. clocks = <&clks IMX6QDL_CLK_CKO>;
  194. clock-names = "xvclk";
  195. reg = <0x30>;
  196. powerdown-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>;
  197. reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
  198. status = "okay";
  199. port {
  200. ov2659_to_ipu1_csi0_mux: endpoint {
  201. remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
  202. link-frequencies = /bits/ 64 <70000000>;
  203. bus-width = <8>;
  204. hsync-active = <1>;
  205. vsync-active = <1>;
  206. };
  207. };
  208. };
  209. };
  210. &iomuxc {
  211. pinctrl_ecspi1: ecspi1grp {
  212. fsl,pins = <
  213. MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
  214. MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
  215. MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
  216. >;
  217. };
  218. pinctrl_ecspi1_gpio: ecspi1grpgpiogrp {
  219. fsl,pins = <
  220. MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0
  221. MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0
  222. >;
  223. };
  224. pinctrl_enet: enetgrp {
  225. fsl,pins = <
  226. MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
  227. MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
  228. MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
  229. MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
  230. MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
  231. MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
  232. MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
  233. MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
  234. MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
  235. MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
  236. MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
  237. MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
  238. MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
  239. MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
  240. MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
  241. MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
  242. >;
  243. };
  244. pinctrl_hdmi_cec: hdmicecgrp {
  245. fsl,pins = <
  246. MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
  247. >;
  248. };
  249. pinctrl_i2c2: i2c2grp {
  250. fsl,pins = <
  251. MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
  252. MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  253. >;
  254. };
  255. pinctrl_i2c3: i2c3grp {
  256. fsl,pins = <
  257. MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
  258. MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
  259. >;
  260. };
  261. pinctrl_ipu1_csi0: ipu1csi0grp {
  262. fsl,pins = <
  263. MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
  264. MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
  265. MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
  266. MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
  267. MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
  268. MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
  269. MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
  270. MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
  271. MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
  272. MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
  273. MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
  274. >;
  275. };
  276. pinctrl_ov2659: ov2659grp {
  277. fsl,pins = <
  278. MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b0
  279. MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0
  280. MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
  281. >;
  282. };
  283. pinctrl_uart4: uart4grp {
  284. fsl,pins = <
  285. MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
  286. MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
  287. >;
  288. };
  289. pinctrl_usbotg: usbotggrp {
  290. fsl,pins = <
  291. MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
  292. >;
  293. };
  294. pinctrl_usdhc1: usdhc1grp {
  295. fsl,pins = <
  296. MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
  297. MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
  298. MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
  299. MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
  300. MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
  301. MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
  302. >;
  303. };
  304. pinctrl_usdhc1_gpio: usdhc1grpgpiogrp {
  305. fsl,pins = <
  306. MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
  307. >;
  308. };
  309. pinctrl_usdhc2: usdhc2grp {
  310. fsl,pins = <
  311. MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
  312. MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
  313. MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
  314. MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
  315. MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
  316. MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
  317. >;
  318. };
  319. pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
  320. fsl,pins = <
  321. MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
  322. MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
  323. >;
  324. };
  325. pinctrl_usdhc3: usdhc3grp {
  326. fsl,pins = <
  327. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
  328. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
  329. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
  330. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
  331. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
  332. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
  333. MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
  334. MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
  335. MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
  336. MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
  337. >;
  338. };
  339. pinctrl_wdog: wdoggrp {
  340. fsl,pins = <
  341. MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b0
  342. >;
  343. };
  344. pinctrl_gpio_leds: gpioledsgrp {
  345. fsl,pins = <
  346. MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x1b0b0
  347. >;
  348. };
  349. };
  350. &uart4 {
  351. pinctrl-names = "default";
  352. pinctrl-0 = <&pinctrl_uart4>;
  353. status = "okay";
  354. };
  355. &usbh1 {
  356. vbus-supply = <&reg_usb_h1_vbus>;
  357. status = "okay";
  358. };
  359. &usbotg {
  360. vbus-supply = <&reg_usb_otg_vbus>;
  361. pinctrl-names = "default";
  362. pinctrl-0 = <&pinctrl_usbotg>;
  363. disable-over-current;
  364. status = "okay";
  365. };
  366. &usdhc1 {
  367. pinctrl-names = "default";
  368. pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
  369. bus-width = <4>;
  370. cd-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
  371. status = "okay";
  372. };
  373. &usdhc2 {
  374. pinctrl-names = "default";
  375. pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
  376. bus-width = <4>;
  377. cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
  378. wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
  379. status = "disabled";
  380. };
  381. &usdhc3 {
  382. pinctrl-names = "default";
  383. pinctrl-0 = <&pinctrl_usdhc3>;
  384. bus-width = <8>;
  385. non-removable;
  386. no-1-8-v;
  387. status = "okay";
  388. };
  389. &wdog1 {
  390. status = "disabled";
  391. };
  392. &wdog2 {
  393. pinctrl-names = "default";
  394. pinctrl-0 = <&pinctrl_wdog>;
  395. fsl,ext-reset-output;
  396. status = "okay";
  397. };