imx6qdl-dfi-fs700-m60.dtsi 4.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. #include <dt-bindings/gpio/gpio.h>
  3. / {
  4. regulators {
  5. compatible = "simple-bus";
  6. #address-cells = <1>;
  7. #size-cells = <0>;
  8. dummy_reg: regulator@0 {
  9. compatible = "regulator-fixed";
  10. reg = <0>;
  11. regulator-name = "dummy-supply";
  12. };
  13. reg_usb_otg_vbus: regulator@1 {
  14. compatible = "regulator-fixed";
  15. reg = <1>;
  16. regulator-name = "usb_otg_vbus";
  17. regulator-min-microvolt = <5000000>;
  18. regulator-max-microvolt = <5000000>;
  19. gpio = <&gpio3 22 0>;
  20. enable-active-high;
  21. };
  22. };
  23. chosen {
  24. stdout-path = &uart1;
  25. };
  26. };
  27. &ecspi3 {
  28. cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
  29. pinctrl-names = "default";
  30. pinctrl-0 = <&pinctrl_ecspi3>;
  31. status = "okay";
  32. flash: flash@0 {
  33. #address-cells = <1>;
  34. #size-cells = <1>;
  35. compatible = "sst,sst25vf040b", "jedec,spi-nor";
  36. spi-max-frequency = <20000000>;
  37. reg = <0>;
  38. };
  39. };
  40. &fec {
  41. pinctrl-names = "default";
  42. pinctrl-0 = <&pinctrl_enet>;
  43. status = "okay";
  44. phy-mode = "rgmii";
  45. };
  46. &iomuxc {
  47. pinctrl-names = "default";
  48. pinctrl-0 = <&pinctrl_hog>;
  49. imx6qdl-dfi-fs700-m60 {
  50. pinctrl_hog: hoggrp {
  51. fsl,pins = <
  52. MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000
  53. MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x80000000 /* PMIC irq */
  54. MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x80000000 /* MAX11801 irq */
  55. MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x000030b0 /* Backlight enable */
  56. >;
  57. };
  58. pinctrl_enet: enetgrp {
  59. fsl,pins = <
  60. MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
  61. MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
  62. MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
  63. MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
  64. MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
  65. MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
  66. MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
  67. MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
  68. MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
  69. MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
  70. MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
  71. MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
  72. MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
  73. MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
  74. MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
  75. MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
  76. >;
  77. };
  78. pinctrl_i2c2: i2c2grp {
  79. fsl,pins = <
  80. MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
  81. MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
  82. >;
  83. };
  84. pinctrl_uart1: uart1grp {
  85. fsl,pins = <
  86. MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
  87. MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
  88. >;
  89. };
  90. pinctrl_usbotg: usbotggrp {
  91. fsl,pins = <
  92. MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
  93. >;
  94. };
  95. pinctrl_usdhc2: usdhc2grp {
  96. fsl,pins = <
  97. MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
  98. MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
  99. MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
  100. MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
  101. MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
  102. MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
  103. MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 /* card detect */
  104. >;
  105. };
  106. pinctrl_usdhc3: usdhc3grp {
  107. fsl,pins = <
  108. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
  109. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
  110. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
  111. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
  112. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
  113. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
  114. >;
  115. };
  116. pinctrl_usdhc4: usdhc4grp {
  117. fsl,pins = <
  118. MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
  119. MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
  120. MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
  121. MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
  122. MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
  123. MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
  124. MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
  125. MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
  126. MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
  127. MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
  128. >;
  129. };
  130. pinctrl_ecspi3: ecspi3grp {
  131. fsl,pins = <
  132. MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
  133. MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
  134. MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
  135. MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
  136. >;
  137. };
  138. };
  139. };
  140. &i2c2 {
  141. pinctrl-names = "default";
  142. pinctrl-0 = <&pinctrl_i2c2>;
  143. status = "okay";
  144. };
  145. &uart1 {
  146. pinctrl-names = "default";
  147. pinctrl-0 = <&pinctrl_uart1>;
  148. status = "okay";
  149. };
  150. &usbh1 {
  151. status = "okay";
  152. };
  153. &usbotg {
  154. vbus-supply = <&reg_usb_otg_vbus>;
  155. pinctrl-names = "default";
  156. pinctrl-0 = <&pinctrl_usbotg>;
  157. disable-over-current;
  158. dr_mode = "host";
  159. status = "okay";
  160. };
  161. &usdhc2 { /* module slot */
  162. pinctrl-names = "default";
  163. pinctrl-0 = <&pinctrl_usdhc2>;
  164. cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
  165. status = "okay";
  166. };
  167. &usdhc3 { /* baseboard slot */
  168. pinctrl-names = "default";
  169. pinctrl-0 = <&pinctrl_usdhc3>;
  170. };
  171. &usdhc4 { /* eMMC */
  172. pinctrl-names = "default";
  173. pinctrl-0 = <&pinctrl_usdhc4>;
  174. bus-width = <8>;
  175. non-removable;
  176. status = "okay";
  177. };