imx6qdl-apf6.dtsi 3.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR MIT
  2. //
  3. // Copyright 2015 Armadeus Systems <[email protected]>
  4. #include <dt-bindings/gpio/gpio.h>
  5. #include <dt-bindings/interrupt-controller/irq.h>
  6. / {
  7. reg_1p8v: regulator-1p8v {
  8. compatible = "regulator-fixed";
  9. regulator-name = "1P8V";
  10. regulator-min-microvolt = <1800000>;
  11. regulator-max-microvolt = <1800000>;
  12. regulator-always-on;
  13. vin-supply = <&reg_3p3v>;
  14. };
  15. usdhc1_pwrseq: usdhc1-pwrseq {
  16. compatible = "mmc-pwrseq-simple";
  17. reset-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
  18. post-power-on-delay-ms = <15>;
  19. power-off-delay-us = <70>;
  20. };
  21. };
  22. &fec {
  23. pinctrl-names = "default";
  24. pinctrl-0 = <&pinctrl_enet>;
  25. phy-mode = "rgmii-id";
  26. phy-reset-duration = <10>;
  27. phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
  28. phy-handle = <&ethphy1>;
  29. status = "okay";
  30. mdio {
  31. #address-cells = <1>;
  32. #size-cells = <0>;
  33. ethphy1: ethernet-phy@1 {
  34. compatible = "ethernet-phy-ieee802.3-c22";
  35. reg = <1>;
  36. interrupt-parent = <&gpio1>;
  37. interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
  38. status = "okay";
  39. };
  40. };
  41. };
  42. /* Bluetooth */
  43. &uart2 {
  44. pinctrl-names = "default";
  45. pinctrl-0 = <&pinctrl_uart2>;
  46. uart-has-rtscts;
  47. status = "okay";
  48. };
  49. /* Wi-Fi */
  50. &usdhc1 {
  51. pinctrl-names = "default";
  52. pinctrl-0 = <&pinctrl_usdhc1>;
  53. bus-width = <4>;
  54. mmc-pwrseq = <&usdhc1_pwrseq>;
  55. vmmc-supply = <&reg_3p3v>;
  56. vqmmc-supply = <&reg_1p8v>;
  57. cap-power-off-card;
  58. keep-power-in-suspend;
  59. non-removable;
  60. status = "okay";
  61. #address-cells = <1>;
  62. #size-cells = <0>;
  63. wlcore: wlcore@2 {
  64. compatible = "ti,wl1271";
  65. reg = <2>;
  66. interrupt-parent = <&gpio2>;
  67. interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
  68. ref-clock-frequency = <38400000>;
  69. tcxo-clock-frequency = <38400000>;
  70. };
  71. };
  72. /* eMMC */
  73. &usdhc3 {
  74. pinctrl-names = "default";
  75. pinctrl-0 = <&pinctrl_usdhc3>;
  76. bus-width = <8>;
  77. no-1-8-v;
  78. non-removable;
  79. status = "okay";
  80. };
  81. &iomuxc {
  82. pinctrl_enet: enetgrp {
  83. fsl,pins = <
  84. MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0
  85. MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
  86. MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
  87. MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x130b0
  88. MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x130b0
  89. MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
  90. MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
  91. MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
  92. MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
  93. MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
  94. MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
  95. MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x13030
  96. MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
  97. MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030
  98. MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1f030
  99. MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1f030
  100. MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
  101. >;
  102. };
  103. pinctrl_uart2: uart2grp {
  104. fsl,pins = <
  105. MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b0
  106. MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b0
  107. MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b0
  108. MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b0
  109. MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x130b0 /* BT_EN */
  110. >;
  111. };
  112. pinctrl_usdhc1: usdhc1grp {
  113. fsl,pins = <
  114. MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
  115. MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
  116. MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
  117. MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
  118. MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
  119. MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
  120. MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x130b0 /* WL_EN */
  121. MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x130b0 /* WL_IRQ */
  122. >;
  123. };
  124. pinctrl_usdhc3: usdhc3grp {
  125. fsl,pins = <
  126. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
  127. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
  128. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
  129. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
  130. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
  131. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
  132. MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
  133. MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
  134. MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
  135. MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
  136. >;
  137. };
  138. };