imx6q-tbs2910.dts 8.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR MIT
  2. //
  3. // Copyright 2014 Soeren Moch <[email protected]>
  4. /dts-v1/;
  5. #include "imx6q.dtsi"
  6. #include <dt-bindings/gpio/gpio.h>
  7. #include <dt-bindings/input/input.h>
  8. / {
  9. model = "TBS2910 Matrix ARM mini PC";
  10. compatible = "tbs,imx6q-tbs2910", "fsl,imx6q";
  11. chosen {
  12. stdout-path = &uart1;
  13. };
  14. aliases {
  15. mmc0 = &usdhc2;
  16. mmc1 = &usdhc3;
  17. mmc2 = &usdhc4;
  18. /delete-property/ mmc3;
  19. };
  20. memory@10000000 {
  21. device_type = "memory";
  22. reg = <0x10000000 0x80000000>;
  23. };
  24. fan {
  25. compatible = "gpio-fan";
  26. pinctrl-names = "default";
  27. pinctrl-0 = <&pinctrl_gpio_fan>;
  28. gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
  29. gpio-fan,speed-map = <0 0
  30. 3000 1>;
  31. };
  32. ir_recv {
  33. compatible = "gpio-ir-receiver";
  34. gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
  35. pinctrl-names = "default";
  36. pinctrl-0 = <&pinctrl_ir>;
  37. };
  38. leds {
  39. compatible = "gpio-leds";
  40. pinctrl-names = "default";
  41. pinctrl-0 = <&pinctrl_gpio_leds>;
  42. led-blue {
  43. label = "blue_status_led";
  44. gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
  45. default-state = "keep";
  46. };
  47. };
  48. reg_2p5v: regulator-2p5v {
  49. compatible = "regulator-fixed";
  50. regulator-name = "2P5V";
  51. regulator-min-microvolt = <2500000>;
  52. regulator-max-microvolt = <2500000>;
  53. };
  54. reg_3p3v: regulator-3p3v {
  55. compatible = "regulator-fixed";
  56. regulator-name = "3P3V";
  57. regulator-min-microvolt = <3300000>;
  58. regulator-max-microvolt = <3300000>;
  59. };
  60. reg_5p0v: regulator-5p0v {
  61. compatible = "regulator-fixed";
  62. regulator-name = "5P0V";
  63. regulator-min-microvolt = <5000000>;
  64. regulator-max-microvolt = <5000000>;
  65. };
  66. sound-sgtl5000 {
  67. audio-codec = <&sgtl5000>;
  68. audio-routing =
  69. "MIC_IN", "Mic Jack",
  70. "Mic Jack", "Mic Bias",
  71. "Headphone Jack", "HP_OUT";
  72. compatible = "fsl,imx-audio-sgtl5000";
  73. model = "On-board Codec";
  74. mux-ext-port = <3>;
  75. mux-int-port = <1>;
  76. ssi-controller = <&ssi1>;
  77. };
  78. sound-spdif {
  79. compatible = "fsl,imx-audio-spdif";
  80. model = "On-board SPDIF";
  81. spdif-controller = <&spdif>;
  82. spdif-out;
  83. };
  84. };
  85. &audmux {
  86. status = "okay";
  87. };
  88. &fec {
  89. pinctrl-names = "default";
  90. pinctrl-0 = <&pinctrl_enet>;
  91. phy-mode = "rgmii-id";
  92. phy-handle = <&phy>;
  93. status = "okay";
  94. mdio {
  95. #address-cells = <1>;
  96. #size-cells = <0>;
  97. phy: ethernet-phy@4 {
  98. reg = <4>;
  99. qca,clk-out-frequency = <125000000>;
  100. reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
  101. reset-assert-us = <10000>;
  102. };
  103. };
  104. };
  105. &hdmi {
  106. pinctrl-names = "default";
  107. pinctrl-0 = <&pinctrl_hdmi>;
  108. ddc-i2c-bus = <&i2c2>;
  109. status = "okay";
  110. };
  111. &i2c1 {
  112. clock-frequency = <100000>;
  113. pinctrl-names = "default";
  114. pinctrl-0 = <&pinctrl_i2c1>;
  115. status = "okay";
  116. sgtl5000: sgtl5000@a {
  117. clocks = <&clks IMX6QDL_CLK_CKO>;
  118. compatible = "fsl,sgtl5000";
  119. pinctrl-names = "default";
  120. pinctrl-0 = <&pinctrl_sgtl5000>;
  121. reg = <0x0a>;
  122. VDDA-supply = <&reg_2p5v>;
  123. VDDIO-supply = <&reg_3p3v>;
  124. };
  125. };
  126. &i2c2 {
  127. clock-frequency = <100000>;
  128. pinctrl-names = "default";
  129. pinctrl-0 = <&pinctrl_i2c2>;
  130. status = "okay";
  131. };
  132. &i2c3 {
  133. clock-frequency = <100000>;
  134. pinctrl-names = "default";
  135. pinctrl-0 = <&pinctrl_i2c3>;
  136. status = "okay";
  137. rtc: rtc@68 {
  138. compatible = "dallas,ds1307";
  139. reg = <0x68>;
  140. };
  141. };
  142. &pcie {
  143. pinctrl-names = "default";
  144. pinctrl-0 = <&pinctrl_pcie>;
  145. reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
  146. status = "okay";
  147. };
  148. &sata {
  149. fsl,transmit-level-mV = <1104>;
  150. fsl,transmit-boost-mdB = <3330>;
  151. fsl,transmit-atten-16ths = <16>;
  152. fsl,receive-eq-mdB = <3000>;
  153. status = "okay";
  154. };
  155. &snvs_poweroff {
  156. status = "okay";
  157. };
  158. &spdif {
  159. pinctrl-names = "default";
  160. pinctrl-0 = <&pinctrl_spdif>;
  161. status = "okay";
  162. };
  163. &ssi1 {
  164. status = "okay";
  165. };
  166. &uart1 {
  167. pinctrl-names = "default";
  168. pinctrl-0 = <&pinctrl_uart1>;
  169. status = "okay";
  170. };
  171. &uart2 {
  172. pinctrl-names = "default";
  173. pinctrl-0 = <&pinctrl_uart2>;
  174. status = "okay";
  175. };
  176. &usbh1 {
  177. vbus-supply = <&reg_5p0v>;
  178. status = "okay";
  179. };
  180. &usbotg {
  181. vbus-supply = <&reg_5p0v>;
  182. pinctrl-names = "default";
  183. pinctrl-0 = <&pinctrl_usbotg>;
  184. disable-over-current;
  185. status = "okay";
  186. };
  187. &usdhc2 {
  188. pinctrl-names = "default";
  189. pinctrl-0 = <&pinctrl_usdhc2>;
  190. bus-width = <4>;
  191. cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
  192. vmmc-supply = <&reg_3p3v>;
  193. vqmmc-supply = <&reg_3p3v>;
  194. voltage-ranges = <3300 3300>;
  195. no-1-8-v;
  196. status = "okay";
  197. };
  198. &usdhc3 {
  199. pinctrl-names = "default";
  200. pinctrl-0 = <&pinctrl_usdhc3>;
  201. bus-width = <4>;
  202. cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
  203. wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
  204. vmmc-supply = <&reg_3p3v>;
  205. vqmmc-supply = <&reg_3p3v>;
  206. voltage-ranges = <3300 3300>;
  207. no-1-8-v;
  208. status = "okay";
  209. };
  210. &usdhc4 {
  211. pinctrl-names = "default";
  212. pinctrl-0 = <&pinctrl_usdhc4>;
  213. bus-width = <8>;
  214. vmmc-supply = <&reg_3p3v>;
  215. vqmmc-supply = <&reg_3p3v>;
  216. voltage-ranges = <3300 3300>;
  217. non-removable;
  218. no-1-8-v;
  219. status = "okay";
  220. };
  221. &iomuxc {
  222. pinctrl_enet: enetgrp {
  223. fsl,pins = <
  224. MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
  225. MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
  226. MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
  227. MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
  228. MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
  229. MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
  230. MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
  231. MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
  232. MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
  233. MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
  234. MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
  235. MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
  236. MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
  237. MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
  238. MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
  239. MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
  240. MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b059
  241. >;
  242. };
  243. pinctrl_gpio_fan: gpiofangrp {
  244. fsl,pins = <
  245. MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x130b1
  246. >;
  247. };
  248. pinctrl_gpio_leds: gpioledsgrp {
  249. fsl,pins = <
  250. MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b1
  251. >;
  252. };
  253. pinctrl_hdmi: hdmigrp {
  254. fsl,pins = <
  255. MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
  256. >;
  257. };
  258. pinctrl_i2c1: i2c1grp {
  259. fsl,pins = <
  260. MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
  261. MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
  262. >;
  263. };
  264. pinctrl_i2c2: i2c2grp {
  265. fsl,pins = <
  266. MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
  267. MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  268. >;
  269. };
  270. pinctrl_i2c3: i2c3grp {
  271. fsl,pins = <
  272. MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
  273. MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
  274. >;
  275. };
  276. pinctrl_ir: irgrp {
  277. fsl,pins = <
  278. MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x17059
  279. >;
  280. };
  281. pinctrl_pcie: pciegrp {
  282. fsl,pins = <
  283. MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x17059
  284. >;
  285. };
  286. pinctrl_sgtl5000: sgtl5000grp {
  287. fsl,pins = <
  288. MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
  289. MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
  290. MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
  291. MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
  292. MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
  293. >;
  294. };
  295. pinctrl_spdif: spdifgrp {
  296. fsl,pins = <MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x13091
  297. >;
  298. };
  299. pinctrl_uart1: uart1grp {
  300. fsl,pins = <
  301. MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
  302. MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
  303. >;
  304. };
  305. pinctrl_uart2: uart2grp {
  306. fsl,pins = <
  307. MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
  308. MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
  309. >;
  310. };
  311. pinctrl_usbotg: usbotggrp {
  312. fsl,pins = <
  313. MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
  314. >;
  315. };
  316. pinctrl_usdhc2: usdhc2grp {
  317. fsl,pins = <
  318. MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
  319. MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
  320. MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
  321. MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
  322. MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
  323. MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
  324. MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x17059
  325. >;
  326. };
  327. pinctrl_usdhc3: usdhc3grp {
  328. fsl,pins = <
  329. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
  330. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
  331. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
  332. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
  333. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
  334. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
  335. MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x17059
  336. MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x17059
  337. >;
  338. };
  339. pinctrl_usdhc4: usdhc4grp {
  340. fsl,pins = <
  341. MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
  342. MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
  343. MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
  344. MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
  345. MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
  346. MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
  347. MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
  348. MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
  349. MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
  350. MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
  351. >;
  352. };
  353. };