imx6q-kp.dtsi 9.6 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Copyright 2018
  4. * Lukasz Majewski, DENX Software Engineering, [email protected]
  5. */
  6. /dts-v1/;
  7. #include "imx6q.dtsi"
  8. #include <dt-bindings/gpio/gpio.h>
  9. #include <dt-bindings/pwm/pwm.h>
  10. #include <dt-bindings/sound/fsl-imx-audmux.h>
  11. / {
  12. backlight_lcd: backlight-lcd {
  13. compatible = "pwm-backlight";
  14. pwms = <&pwm1 0 5000000>;
  15. brightness-levels = <0 255>;
  16. num-interpolated-steps = <255>;
  17. default-brightness-level = <250>;
  18. };
  19. beeper {
  20. compatible = "pwm-beeper";
  21. pwms = <&pwm2 0 500000>;
  22. };
  23. lcd_display: display {
  24. compatible = "fsl,imx-parallel-display";
  25. #address-cells = <1>;
  26. #size-cells = <0>;
  27. interface-pix-fmt = "rgb24";
  28. pinctrl-names = "default";
  29. pinctrl-0 = <&pinctrl_ipu1>;
  30. port@0 {
  31. reg = <0>;
  32. lcd_display_in: endpoint {
  33. remote-endpoint = <&ipu1_di0_disp0>;
  34. };
  35. };
  36. port@1 {
  37. reg = <1>;
  38. lcd_display_out: endpoint {
  39. remote-endpoint = <&lcd_panel_in>;
  40. };
  41. };
  42. };
  43. lcd_panel: lcd-panel {
  44. compatible = "auo,g070vvn01";
  45. backlight = <&backlight_lcd>;
  46. power-supply = <&reg_display>;
  47. port {
  48. lcd_panel_in: endpoint {
  49. remote-endpoint = <&lcd_display_out>;
  50. };
  51. };
  52. };
  53. leds {
  54. compatible = "gpio-leds";
  55. led-green {
  56. label = "led1";
  57. gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
  58. linux,default-trigger = "gpio";
  59. default-state = "off";
  60. };
  61. led-red {
  62. label = "led0";
  63. gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
  64. linux,default-trigger = "gpio";
  65. default-state = "off";
  66. };
  67. };
  68. reg_3p3v: regulator-3p3v {
  69. compatible = "regulator-fixed";
  70. regulator-name = "3P3V";
  71. regulator-min-microvolt = <3300000>;
  72. regulator-max-microvolt = <3300000>;
  73. regulator-always-on;
  74. };
  75. reg_audio: regulator-audio {
  76. compatible = "regulator-fixed";
  77. regulator-name = "sgtl5000-supply";
  78. gpio = <&gpio6 31 GPIO_ACTIVE_HIGH>;
  79. enable-active-high;
  80. regulator-always-on;
  81. };
  82. reg_display: regulator-display {
  83. compatible = "regulator-fixed";
  84. regulator-name = "display-supply";
  85. regulator-min-microvolt = <3300000>;
  86. regulator-max-microvolt = <3300000>;
  87. regulator-always-on;
  88. };
  89. reg_usb_h1_vbus: regulator-usb_h1_vbus {
  90. compatible = "regulator-fixed";
  91. regulator-name = "usb_h1_vbus";
  92. regulator-min-microvolt = <5000000>;
  93. regulator-max-microvolt = <5000000>;
  94. enable-active-high;
  95. };
  96. sound {
  97. compatible = "simple-audio-card";
  98. simple-audio-card,name = "imx6q-sgtl5000-audio";
  99. simple-audio-card,format = "i2s";
  100. simple-audio-card,bitclock-master = <&codec_dai>;
  101. simple-audio-card,frame-master = <&codec_dai>;
  102. cpu_dai: simple-audio-card,cpu {
  103. sound-dai = <&ssi1>;
  104. };
  105. codec_dai: simple-audio-card,codec {
  106. sound-dai = <&sgtl5000>;
  107. };
  108. };
  109. };
  110. &audmux {
  111. pinctrl-names = "default";
  112. pinctrl-0 = <&pinctrl_audmux>;
  113. status = "okay";
  114. ssi1 {
  115. fsl,audmux-port = <0>;
  116. fsl,port-config = <
  117. (IMX_AUDMUX_V2_PTCR_SYN |
  118. IMX_AUDMUX_V2_PTCR_TFSEL(2) |
  119. IMX_AUDMUX_V2_PTCR_TCSEL(2) |
  120. IMX_AUDMUX_V2_PTCR_TFSDIR |
  121. IMX_AUDMUX_V2_PTCR_TCLKDIR)
  122. IMX_AUDMUX_V2_PDCR_RXDSEL(2)
  123. >;
  124. };
  125. aud3 {
  126. fsl,audmux-port = <2>;
  127. fsl,port-config = <
  128. IMX_AUDMUX_V2_PTCR_SYN
  129. IMX_AUDMUX_V2_PDCR_RXDSEL(0)
  130. >;
  131. };
  132. };
  133. &can1 {
  134. pinctrl-names = "default";
  135. pinctrl-0 = <&pinctrl_flexcan1>;
  136. };
  137. &can2 {
  138. pinctrl-names = "default";
  139. pinctrl-0 = <&pinctrl_flexcan2>;
  140. };
  141. &fec {
  142. pinctrl-names = "default";
  143. pinctrl-0 = <&pinctrl_enet>;
  144. phy-mode = "rgmii";
  145. fsl,magic-packet;
  146. status = "okay";
  147. };
  148. &i2c1 {
  149. clock-frequency = <400000>;
  150. pinctrl-names = "default";
  151. pinctrl-0 = <&pinctrl_i2c1>;
  152. status = "okay";
  153. touchscreen@5d {
  154. compatible = "goodix,gt911";
  155. reg = <0x5d>;
  156. pinctrl-names = "default";
  157. pinctrl-0 = <&pinctrl_ts>;
  158. interrupt-parent = <&gpio1>;
  159. interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
  160. irq-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
  161. reset-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
  162. };
  163. ds1307: rtc@32 {
  164. compatible = "dallas,ds1307";
  165. reg = <0x32>;
  166. };
  167. };
  168. &i2c2 {
  169. clock-frequency = <400000>;
  170. pinctrl-names = "default";
  171. pinctrl-0 = <&pinctrl_i2c2>;
  172. status = "okay";
  173. sgtl5000: audio-codec@a {
  174. compatible = "fsl,sgtl5000";
  175. #sound-dai-cells = <0>;
  176. reg = <0x0a>;
  177. pinctrl-names = "default";
  178. pinctrl-0 = <&pinctrl_codec>;
  179. clocks = <&clks IMX6QDL_CLK_CKO>;
  180. VDDA-supply = <&reg_3p3v>;
  181. VDDIO-supply = <&reg_3p3v>;
  182. };
  183. };
  184. &iomuxc {
  185. pinctrl_audmux: audmuxgrp {
  186. fsl,pins = <
  187. MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
  188. MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
  189. MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
  190. MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
  191. >;
  192. };
  193. pinctrl_codec: codecgrp {
  194. fsl,pins = <
  195. MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0
  196. /* sgtl5000 sys_mclk clock routed to CLKO1 */
  197. MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0
  198. >;
  199. };
  200. pinctrl_enet: enetgrp {
  201. fsl,pins = <
  202. MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
  203. MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
  204. MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
  205. MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
  206. MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
  207. MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
  208. MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
  209. MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
  210. MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
  211. MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
  212. MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
  213. MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
  214. MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
  215. MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
  216. MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
  217. MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
  218. >;
  219. };
  220. pinctrl_flexcan1: can1grp {
  221. fsl,pins = <
  222. MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
  223. MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
  224. >;
  225. };
  226. pinctrl_flexcan2: can2grp {
  227. fsl,pins = <
  228. MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
  229. MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
  230. >;
  231. };
  232. pinctrl_i2c1: i2c1grp {
  233. fsl,pins = <
  234. MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
  235. MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
  236. >;
  237. };
  238. pinctrl_i2c2: i2c2grp {
  239. fsl,pins = <
  240. MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
  241. MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  242. >;
  243. };
  244. pinctrl_ipu1: ipu1grp {
  245. fsl,pins = <
  246. MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
  247. MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
  248. MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
  249. MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
  250. MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
  251. MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
  252. MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
  253. MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
  254. MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
  255. MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
  256. MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
  257. MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
  258. MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
  259. MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
  260. MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
  261. MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
  262. MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
  263. MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
  264. MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
  265. MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
  266. MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
  267. MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
  268. MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
  269. MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
  270. MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
  271. MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
  272. MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
  273. MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
  274. >;
  275. };
  276. pinctrl_pwm1: pwm1grp {
  277. fsl,pins = <
  278. MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
  279. >;
  280. };
  281. pinctrl_pwm2: pwm2grp {
  282. fsl,pins = <
  283. MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
  284. >;
  285. };
  286. pinctrl_ts: tsgrp {
  287. fsl,pins = <
  288. MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
  289. MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0
  290. >;
  291. };
  292. pinctrl_uart1: uart1grp {
  293. fsl,pins = <
  294. MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
  295. MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
  296. >;
  297. };
  298. pinctrl_uart2: uart2grp {
  299. fsl,pins = <
  300. MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
  301. MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
  302. MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x1b0b1
  303. MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x1b0b1
  304. >;
  305. };
  306. pinctrl_usdhc2: usdhc2grp {
  307. fsl,pins = <
  308. MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
  309. MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
  310. MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
  311. MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
  312. MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
  313. MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
  314. >;
  315. };
  316. pinctrl_usdhc4: usdhc4grp {
  317. fsl,pins = <
  318. MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
  319. MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
  320. MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
  321. MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
  322. MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
  323. MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
  324. MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
  325. MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
  326. MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
  327. MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
  328. >;
  329. };
  330. };
  331. &pwm1 {
  332. #pwm-cells = <2>;
  333. pinctrl-names = "default";
  334. pinctrl-0 = <&pinctrl_pwm1>;
  335. status = "okay";
  336. };
  337. &pwm2 {
  338. #pwm-cells = <2>;
  339. pinctrl-names = "default";
  340. pinctrl-0 = <&pinctrl_pwm2>;
  341. status = "okay";
  342. };
  343. &ssi1 {
  344. status = "okay";
  345. };
  346. &uart1 {
  347. pinctrl-names = "default";
  348. pinctrl-0 = <&pinctrl_uart1>;
  349. status = "okay";
  350. };
  351. &uart2 {
  352. pinctrl-names = "default";
  353. pinctrl-0 = <&pinctrl_uart2>;
  354. uart-has-rtscts;
  355. };
  356. &usbh1 {
  357. status = "okay";
  358. };
  359. &usdhc2 {
  360. pinctrl-names = "default";
  361. pinctrl-0 = <&pinctrl_usdhc2>;
  362. bus-width = <4>;
  363. cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
  364. status = "okay";
  365. };
  366. &usdhc4 {
  367. pinctrl-names = "default";
  368. pinctrl-0 = <&pinctrl_usdhc4>;
  369. bus-width = <8>;
  370. non-removable;
  371. no-1-8-v;
  372. keep-power-in-suspend;
  373. status = "okay";
  374. };
  375. &wdog1 {
  376. status = "okay";
  377. };