imx6dl-riotboard.dts 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright 2014 Iain Paton <[email protected]>
  4. */
  5. /dts-v1/;
  6. #include "imx6dl.dtsi"
  7. #include <dt-bindings/gpio/gpio.h>
  8. / {
  9. model = "RIoTboard i.MX6S";
  10. compatible = "riot,imx6s-riotboard", "fsl,imx6dl";
  11. memory@10000000 {
  12. device_type = "memory";
  13. reg = <0x10000000 0x40000000>;
  14. };
  15. chosen {
  16. stdout-path = "serial1:115200n8";
  17. };
  18. leds {
  19. compatible = "gpio-leds";
  20. pinctrl-names = "default";
  21. pinctrl-0 = <&pinctrl_led>;
  22. led0: led-user1 {
  23. label = "user1";
  24. gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
  25. default-state = "on";
  26. linux,default-trigger = "heartbeat";
  27. };
  28. led1: led-user2 {
  29. label = "user2";
  30. gpios = <&gpio3 28 GPIO_ACTIVE_LOW>;
  31. default-state = "off";
  32. };
  33. };
  34. sound {
  35. compatible = "fsl,imx-audio-sgtl5000";
  36. model = "imx6-riotboard-sgtl5000";
  37. ssi-controller = <&ssi1>;
  38. audio-codec = <&codec>;
  39. audio-routing =
  40. "MIC_IN", "Mic Jack",
  41. "Mic Jack", "Mic Bias",
  42. "Headphone Jack", "HP_OUT";
  43. mux-int-port = <1>;
  44. mux-ext-port = <3>;
  45. };
  46. reg_2p5v: regulator-2p5v {
  47. compatible = "regulator-fixed";
  48. regulator-name = "2P5V";
  49. regulator-min-microvolt = <2500000>;
  50. regulator-max-microvolt = <2500000>;
  51. };
  52. reg_3p3v: regulator-3p3v {
  53. compatible = "regulator-fixed";
  54. regulator-name = "3P3V";
  55. regulator-min-microvolt = <3300000>;
  56. regulator-max-microvolt = <3300000>;
  57. };
  58. reg_usb_otg_vbus: regulator-usbotgvbus {
  59. compatible = "regulator-fixed";
  60. regulator-name = "usb_otg_vbus";
  61. regulator-min-microvolt = <5000000>;
  62. regulator-max-microvolt = <5000000>;
  63. gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
  64. };
  65. };
  66. &audmux {
  67. pinctrl-names = "default";
  68. pinctrl-0 = <&pinctrl_audmux>;
  69. status = "okay";
  70. };
  71. &clks {
  72. fsl,pmic-stby-poweroff;
  73. };
  74. &fec {
  75. pinctrl-names = "default";
  76. pinctrl-0 = <&pinctrl_enet>;
  77. phy-mode = "rgmii-id";
  78. phy-handle = <&rgmii_phy>;
  79. /delete-property/ interrupts;
  80. interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
  81. <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
  82. fsl,err006687-workaround-present;
  83. status = "okay";
  84. mdio {
  85. #address-cells = <1>;
  86. #size-cells = <0>;
  87. /* Atheros AR8035 PHY */
  88. rgmii_phy: ethernet-phy@4 {
  89. reg = <4>;
  90. interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>;
  91. reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
  92. reset-assert-us = <10000>;
  93. reset-deassert-us = <1000>;
  94. qca,smarteee-tw-us-1g = <24>;
  95. qca,clk-out-frequency = <125000000>;
  96. };
  97. };
  98. };
  99. &gpio1 {
  100. gpio-line-names =
  101. "", "", "SD2_WP", "", "SD2_CD", "I2C3_SCL",
  102. "I2C3_SDA", "I2C4_SCL",
  103. "I2C4_SDA", "", "", "", "", "", "", "",
  104. "", "PWM3", "", "", "", "", "", "",
  105. "", "", "", "", "", "", "", "";
  106. };
  107. &gpio3 {
  108. gpio-line-names =
  109. "", "", "", "", "", "", "", "",
  110. "", "", "", "", "", "", "", "",
  111. "", "", "", "", "", "", "USB_OTG_VBUS", "",
  112. "UART3_TXD", "UART3_RXD", "", "", "EIM_D28", "", "", "";
  113. };
  114. &gpio4 {
  115. gpio-line-names =
  116. "", "", "", "", "", "", "UART4_TXD", "UART4_RXD",
  117. "UART5_TXD", "UART5_RXD", "", "", "", "", "", "",
  118. "GPIO4_16", "GPIO4_17", "GPIO4_18", "GPIO4_19", "",
  119. "CSPI3_CLK", "CSPI3_MOSI", "CSPI3_MISO",
  120. "CSPI3_CS0", "CSPI3_CS1", "GPIO4_26", "GPIO4_27",
  121. "CSPI3_RDY", "PWM1", "PWM2", "GPIO4_31";
  122. };
  123. &gpio5 {
  124. gpio-line-names =
  125. "", "", "EIM_A25", "", "", "GPIO5_05", "GPIO5_06",
  126. "GPIO5_07",
  127. "GPIO5_08", "CSPI2_CS1", "CSPI2_MOSI", "CSPI2_MISO",
  128. "CSPI2_CS0", "CSPI2_CLK", "", "",
  129. "", "", "", "", "", "", "", "",
  130. "", "", "", "", "", "", "", "";
  131. };
  132. &gpio7 {
  133. gpio-line-names =
  134. "SD3_CD", "SD3_WP", "", "", "", "", "", "",
  135. "", "", "", "", "", "", "", "",
  136. "", "", "", "", "", "", "", "",
  137. "", "", "", "", "", "", "", "";
  138. };
  139. &hdmi {
  140. ddc-i2c-bus = <&i2c2>;
  141. status = "okay";
  142. };
  143. &i2c1 {
  144. clock-frequency = <100000>;
  145. pinctrl-names = "default";
  146. pinctrl-0 = <&pinctrl_i2c1>;
  147. status = "okay";
  148. codec: sgtl5000@a {
  149. compatible = "fsl,sgtl5000";
  150. reg = <0x0a>;
  151. clocks = <&clks IMX6QDL_CLK_CKO>;
  152. VDDA-supply = <&reg_2p5v>;
  153. VDDIO-supply = <&reg_3p3v>;
  154. };
  155. pmic: pf0100@8 {
  156. compatible = "fsl,pfuze100";
  157. reg = <0x08>;
  158. interrupt-parent = <&gpio5>;
  159. interrupts = <16 8>;
  160. fsl,pmic-stby-poweroff;
  161. regulators {
  162. reg_vddcore: sw1ab { /* VDDARM_IN */
  163. regulator-min-microvolt = <300000>;
  164. regulator-max-microvolt = <1875000>;
  165. regulator-always-on;
  166. };
  167. reg_vddsoc: sw1c { /* VDDSOC_IN */
  168. regulator-min-microvolt = <300000>;
  169. regulator-max-microvolt = <1875000>;
  170. regulator-always-on;
  171. };
  172. reg_gen_3v3: sw2 { /* VDDHIGH_IN */
  173. regulator-min-microvolt = <800000>;
  174. regulator-max-microvolt = <3300000>;
  175. regulator-always-on;
  176. };
  177. reg_ddr_1v5a: sw3a { /* NVCC_DRAM, NVCC_RGMII */
  178. regulator-min-microvolt = <400000>;
  179. regulator-max-microvolt = <1975000>;
  180. regulator-always-on;
  181. };
  182. reg_ddr_1v5b: sw3b { /* NVCC_DRAM, NVCC_RGMII */
  183. regulator-min-microvolt = <400000>;
  184. regulator-max-microvolt = <1975000>;
  185. regulator-always-on;
  186. };
  187. reg_ddr_vtt: sw4 { /* MIPI conn */
  188. regulator-min-microvolt = <400000>;
  189. regulator-max-microvolt = <1975000>;
  190. regulator-always-on;
  191. };
  192. reg_5v_600mA: swbst { /* not used */
  193. regulator-min-microvolt = <5000000>;
  194. regulator-max-microvolt = <5150000>;
  195. };
  196. reg_snvs_3v: vsnvs { /* VDD_SNVS_IN */
  197. regulator-min-microvolt = <1500000>;
  198. regulator-max-microvolt = <3000000>;
  199. regulator-always-on;
  200. };
  201. vref_reg: vrefddr { /* VREF_DDR */
  202. regulator-boot-on;
  203. regulator-always-on;
  204. };
  205. reg_vgen1_1v5: vgen1 { /* not used */
  206. regulator-min-microvolt = <800000>;
  207. regulator-max-microvolt = <1550000>;
  208. };
  209. reg_vgen2_1v2_eth: vgen2 { /* pcie ? */
  210. regulator-min-microvolt = <800000>;
  211. regulator-max-microvolt = <1550000>;
  212. regulator-always-on;
  213. };
  214. reg_vgen3_2v8: vgen3 { /* not used */
  215. regulator-min-microvolt = <1800000>;
  216. regulator-max-microvolt = <3300000>;
  217. };
  218. reg_vgen4_1v8: vgen4 { /* NVCC_SD3 */
  219. regulator-min-microvolt = <1800000>;
  220. regulator-max-microvolt = <3300000>;
  221. regulator-always-on;
  222. };
  223. reg_vgen5_2v5_sgtl: vgen5 { /* Pwr LED & 5V0_delayed enable */
  224. regulator-min-microvolt = <1800000>;
  225. regulator-max-microvolt = <3300000>;
  226. regulator-always-on;
  227. };
  228. reg_vgen6_3v3: vgen6 { /* #V#_DELAYED enable, MIPI */
  229. regulator-min-microvolt = <1800000>;
  230. regulator-max-microvolt = <3300000>;
  231. regulator-always-on;
  232. };
  233. };
  234. };
  235. };
  236. &i2c2 {
  237. clock-frequency = <100000>;
  238. pinctrl-names = "default";
  239. pinctrl-0 = <&pinctrl_i2c2>;
  240. status = "okay";
  241. };
  242. &i2c4 {
  243. clock-frequency = <100000>;
  244. pinctrl-names = "default";
  245. pinctrl-0 = <&pinctrl_i2c4>;
  246. clocks = <&clks 116>;
  247. status = "okay";
  248. };
  249. &pwm1 {
  250. pinctrl-names = "default";
  251. pinctrl-0 = <&pinctrl_pwm1>;
  252. status = "okay";
  253. };
  254. &pwm2 {
  255. pinctrl-names = "default";
  256. pinctrl-0 = <&pinctrl_pwm2>;
  257. status = "okay";
  258. };
  259. &pwm3 {
  260. pinctrl-names = "default";
  261. pinctrl-0 = <&pinctrl_pwm3>;
  262. status = "okay";
  263. };
  264. &pwm4 {
  265. pinctrl-names = "default";
  266. pinctrl-0 = <&pinctrl_pwm4>;
  267. status = "okay";
  268. };
  269. &ssi1 {
  270. status = "okay";
  271. };
  272. &uart1 {
  273. pinctrl-names = "default";
  274. pinctrl-0 = <&pinctrl_uart1>;
  275. status = "okay";
  276. };
  277. &uart2 {
  278. pinctrl-names = "default";
  279. pinctrl-0 = <&pinctrl_uart2>;
  280. status = "okay";
  281. };
  282. &uart3 {
  283. pinctrl-names = "default";
  284. pinctrl-0 = <&pinctrl_uart3>;
  285. status = "okay";
  286. };
  287. &uart4 {
  288. pinctrl-names = "default";
  289. pinctrl-0 = <&pinctrl_uart4>;
  290. status = "okay";
  291. };
  292. &uart5 {
  293. pinctrl-names = "default";
  294. pinctrl-0 = <&pinctrl_uart5>;
  295. status = "okay";
  296. };
  297. &usbh1 {
  298. dr_mode = "host";
  299. disable-over-current;
  300. status = "okay";
  301. };
  302. &usbotg {
  303. vbus-supply = <&reg_usb_otg_vbus>;
  304. pinctrl-names = "default";
  305. pinctrl-0 = <&pinctrl_usbotg>;
  306. disable-over-current;
  307. dr_mode = "otg";
  308. status = "okay";
  309. };
  310. &usdhc2 {
  311. pinctrl-names = "default";
  312. pinctrl-0 = <&pinctrl_usdhc2>;
  313. cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
  314. wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
  315. vmmc-supply = <&reg_3p3v>;
  316. status = "okay";
  317. };
  318. &usdhc3 {
  319. pinctrl-names = "default";
  320. pinctrl-0 = <&pinctrl_usdhc3>;
  321. cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
  322. wp-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
  323. vmmc-supply = <&reg_3p3v>;
  324. status = "okay";
  325. };
  326. &usdhc4 {
  327. pinctrl-names = "default";
  328. pinctrl-0 = <&pinctrl_usdhc4>;
  329. vmmc-supply = <&reg_3p3v>;
  330. non-removable;
  331. status = "okay";
  332. };
  333. &iomuxc {
  334. pinctrl-names = "default";
  335. imx6-riotboard {
  336. pinctrl_audmux: audmuxgrp {
  337. fsl,pins = <
  338. MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
  339. MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
  340. MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
  341. MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
  342. MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* CAM_MCLK */
  343. >;
  344. };
  345. pinctrl_ecspi1: ecspi1grp {
  346. fsl,pins = <
  347. MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
  348. MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
  349. MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
  350. MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x000b1 /* CS0 */
  351. >;
  352. };
  353. pinctrl_ecspi2: ecspi2grp {
  354. fsl,pins = <
  355. MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x000b1 /* CS1 */
  356. MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1
  357. MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x100b1
  358. MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000b1 /* CS0 */
  359. MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x100b1
  360. >;
  361. };
  362. pinctrl_ecspi3: ecspi3grp {
  363. fsl,pins = <
  364. MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
  365. MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
  366. MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
  367. MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1 /* CS0 */
  368. MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x000b1 /* CS1 */
  369. >;
  370. };
  371. pinctrl_enet: enetgrp {
  372. fsl,pins = <
  373. MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
  374. MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
  375. MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
  376. MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
  377. MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
  378. MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
  379. MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
  380. MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
  381. MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
  382. MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 /* AR8035 pin strapping: IO voltage: pull up */
  383. MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 /* AR8035 pin strapping: PHYADDR#0: pull down */
  384. MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 /* AR8035 pin strapping: PHYADDR#1: pull down */
  385. MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 /* AR8035 pin strapping: MODE#1: pull up */
  386. MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 /* AR8035 pin strapping: MODE#3: pull up */
  387. MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 /* AR8035 pin strapping: MODE#0: pull down */
  388. MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 /* GPIO16 -> AR8035 25MHz */
  389. MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 /* RGMII_nRST */
  390. MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x180b0 /* AR8035 interrupt */
  391. MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
  392. >;
  393. };
  394. pinctrl_i2c1: i2c1grp {
  395. fsl,pins = <
  396. MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
  397. MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
  398. >;
  399. };
  400. pinctrl_i2c2: i2c2grp {
  401. fsl,pins = <
  402. MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
  403. MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  404. >;
  405. };
  406. pinctrl_i2c3: i2c3grp {
  407. fsl,pins = <
  408. MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
  409. MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
  410. >;
  411. };
  412. pinctrl_i2c4: i2c4grp {
  413. fsl,pins = <
  414. MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1
  415. MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1
  416. >;
  417. };
  418. pinctrl_led: ledgrp {
  419. fsl,pins = <
  420. MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* user led0 */
  421. MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x1b0b1 /* user led1 */
  422. >;
  423. };
  424. pinctrl_pwm1: pwm1grp {
  425. fsl,pins = <
  426. MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1
  427. >;
  428. };
  429. pinctrl_pwm2: pwm2grp {
  430. fsl,pins = <
  431. MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1
  432. >;
  433. };
  434. pinctrl_pwm3: pwm3grp {
  435. fsl,pins = <
  436. MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
  437. >;
  438. };
  439. pinctrl_pwm4: pwm4grp {
  440. fsl,pins = <
  441. MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
  442. >;
  443. };
  444. pinctrl_uart1: uart1grp {
  445. fsl,pins = <
  446. MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
  447. MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
  448. >;
  449. };
  450. pinctrl_uart2: uart2grp {
  451. fsl,pins = <
  452. MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
  453. MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
  454. >;
  455. };
  456. pinctrl_uart3: uart3grp {
  457. fsl,pins = <
  458. MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
  459. MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
  460. >;
  461. };
  462. pinctrl_uart4: uart4grp {
  463. fsl,pins = <
  464. MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
  465. MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
  466. >;
  467. };
  468. pinctrl_uart5: uart5grp {
  469. fsl,pins = <
  470. MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
  471. MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
  472. >;
  473. };
  474. pinctrl_usbotg: usbotggrp {
  475. fsl,pins = <
  476. MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
  477. MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 /* MX6QDL_PAD_EIM_D22__USB_OTG_PWR */
  478. MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0
  479. >;
  480. };
  481. pinctrl_usdhc2: usdhc2grp {
  482. fsl,pins = <
  483. MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
  484. MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
  485. MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
  486. MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
  487. MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
  488. MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
  489. MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* SD2 CD */
  490. MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1f0b0 /* SD2 WP */
  491. >;
  492. };
  493. pinctrl_usdhc3: usdhc3grp {
  494. fsl,pins = <
  495. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
  496. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
  497. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
  498. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
  499. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
  500. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
  501. MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* SD3 CD */
  502. MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* SD3 WP */
  503. >;
  504. };
  505. pinctrl_usdhc4: usdhc4grp {
  506. fsl,pins = <
  507. MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
  508. MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
  509. MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
  510. MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
  511. MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
  512. MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
  513. MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x17059 /* SD4 RST (eMMC) */
  514. >;
  515. };
  516. };
  517. };