imx6dl-alti6p.dts 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. /*
  3. * Copyright (c) 2016 Protonic Holland
  4. * Copyright (c) 2020 Oleksij Rempel <[email protected]>, Pengutronix
  5. */
  6. /dts-v1/;
  7. #include <dt-bindings/gpio/gpio.h>
  8. #include <dt-bindings/leds/common.h>
  9. #include <dt-bindings/sound/fsl-imx-audmux.h>
  10. #include "imx6dl.dtsi"
  11. / {
  12. model = "Altesco I6P Board";
  13. compatible = "alt,alti6p", "fsl,imx6dl";
  14. chosen {
  15. stdout-path = &uart4;
  16. };
  17. clock_ksz8081: clock-ksz8081 {
  18. compatible = "fixed-clock";
  19. #clock-cells = <0>;
  20. clock-frequency = <50000000>;
  21. };
  22. i2c2-mux {
  23. compatible = "i2c-mux";
  24. i2c-parent = <&i2c2>;
  25. mux-controls = <&i2c_mux>;
  26. #address-cells = <1>;
  27. #size-cells = <0>;
  28. i2c@1 {
  29. reg = <1>;
  30. #address-cells = <1>;
  31. #size-cells = <0>;
  32. };
  33. i2c@2 {
  34. reg = <2>;
  35. #address-cells = <1>;
  36. #size-cells = <0>;
  37. };
  38. };
  39. i2c4-mux {
  40. compatible = "i2c-mux";
  41. i2c-parent = <&i2c4>;
  42. mux-controls = <&i2c_mux>;
  43. #address-cells = <1>;
  44. #size-cells = <0>;
  45. i2c@1 {
  46. reg = <1>;
  47. #address-cells = <1>;
  48. #size-cells = <0>;
  49. };
  50. i2c@2 {
  51. reg = <2>;
  52. #address-cells = <1>;
  53. #size-cells = <0>;
  54. };
  55. };
  56. leds {
  57. compatible = "gpio-leds";
  58. pinctrl-names = "default";
  59. pinctrl-0 = <&pinctrl_leds>;
  60. led-debug0 {
  61. function = LED_FUNCTION_STATUS;
  62. gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
  63. linux,default-trigger = "heartbeat";
  64. };
  65. led-debug1 {
  66. function = LED_FUNCTION_SD;
  67. gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
  68. linux,default-trigger = "disk-activity";
  69. };
  70. };
  71. i2c_mux: mux-controller {
  72. compatible = "gpio-mux";
  73. #mux-control-cells = <0>;
  74. pinctrl-names = "default";
  75. pinctrl-0 = <&pinctrl_i2cmux>;
  76. mux-gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>,
  77. <&gpio5 11 GPIO_ACTIVE_HIGH>;
  78. };
  79. reg_1v8: regulator-1v8 {
  80. compatible = "regulator-fixed";
  81. regulator-name = "1v8";
  82. regulator-min-microvolt = <1800000>;
  83. regulator-max-microvolt = <1800000>;
  84. };
  85. reg_3v3: regulator-3v3 {
  86. compatible = "regulator-fixed";
  87. regulator-name = "3v3";
  88. regulator-min-microvolt = <3300000>;
  89. regulator-max-microvolt = <3300000>;
  90. };
  91. reg_5v0: regulator-5v0 {
  92. compatible = "regulator-fixed";
  93. regulator-name = "5v0";
  94. regulator-min-microvolt = <5000000>;
  95. regulator-max-microvolt = <5000000>;
  96. };
  97. reg_h1_vbus: regulator-h1-vbus {
  98. compatible = "regulator-fixed";
  99. regulator-name = "h1-vbus";
  100. regulator-min-microvolt = <5000000>;
  101. regulator-max-microvolt = <5000000>;
  102. gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
  103. enable-active-high;
  104. };
  105. reg_otg_vbus: regulator-otg-vbus {
  106. compatible = "regulator-fixed";
  107. regulator-name = "otg-vbus";
  108. regulator-min-microvolt = <5000000>;
  109. regulator-max-microvolt = <5000000>;
  110. gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
  111. enable-active-high;
  112. };
  113. sound {
  114. compatible = "simple-audio-card";
  115. simple-audio-card,name = "prti6q-sgtl5000";
  116. simple-audio-card,format = "i2s";
  117. simple-audio-card,widgets =
  118. "Microphone", "Microphone Jack",
  119. "Line", "Line In Jack",
  120. "Headphone", "Headphone Jack",
  121. "Speaker", "External Speaker";
  122. simple-audio-card,routing =
  123. "MIC_IN", "Microphone Jack",
  124. "LINE_IN", "Line In Jack",
  125. "Headphone Jack", "HP_OUT",
  126. "External Speaker", "LINE_OUT";
  127. simple-audio-card,cpu {
  128. sound-dai = <&ssi1>;
  129. system-clock-frequency = <0>;
  130. };
  131. simple-audio-card,codec {
  132. sound-dai = <&sgtl5000>;
  133. bitclock-master;
  134. frame-master;
  135. };
  136. };
  137. };
  138. &audmux {
  139. pinctrl-names = "default";
  140. pinctrl-0 = <&pinctrl_audmux>;
  141. status = "okay";
  142. mux-ssi1 {
  143. fsl,audmux-port = <0>;
  144. fsl,port-config = <
  145. IMX_AUDMUX_V2_PTCR_SYN 0
  146. IMX_AUDMUX_V2_PTCR_TFSEL(2) 0
  147. IMX_AUDMUX_V2_PTCR_TCSEL(2) 0
  148. IMX_AUDMUX_V2_PTCR_TFSDIR 0
  149. IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2)
  150. >;
  151. };
  152. mux-pins3 {
  153. fsl,audmux-port = <2>;
  154. fsl,port-config = <
  155. IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0)
  156. 0 IMX_AUDMUX_V2_PDCR_TXRXEN
  157. >;
  158. };
  159. };
  160. &can1 {
  161. pinctrl-names = "default";
  162. pinctrl-0 = <&pinctrl_can1>;
  163. xceiver-supply = <&reg_5v0>;
  164. status = "okay";
  165. };
  166. &ecspi1 {
  167. cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
  168. pinctrl-names = "default";
  169. pinctrl-0 = <&pinctrl_ecspi1>;
  170. status = "okay";
  171. flash@0 {
  172. compatible = "jedec,spi-nor";
  173. reg = <0>;
  174. spi-max-frequency = <20000000>;
  175. };
  176. };
  177. &fec {
  178. pinctrl-names = "default";
  179. pinctrl-0 = <&pinctrl_enet>;
  180. phy-mode = "rmii";
  181. clocks = <&clks IMX6QDL_CLK_ENET>,
  182. <&clks IMX6QDL_CLK_ENET>,
  183. <&clock_ksz8081>;
  184. clock-names = "ipg", "ahb", "ptp";
  185. status = "okay";
  186. mdio {
  187. #address-cells = <1>;
  188. #size-cells = <0>;
  189. /* Microchip KSZ8081RNA PHY */
  190. rgmii_phy: ethernet-phy@0 {
  191. reg = <0>;
  192. interrupts-extended = <&gpio4 30 IRQ_TYPE_LEVEL_LOW>;
  193. reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
  194. reset-assert-us = <10000>;
  195. reset-deassert-us = <300>;
  196. };
  197. };
  198. };
  199. &gpio1 {
  200. gpio-line-names =
  201. "", "SD1_CD", "", "USB_H1_OC", "", "", "", "",
  202. "DEBUG_0", "DEBUG_1", "", "", "", "", "", "",
  203. "", "", "", "", "", "", "", "",
  204. "", "", "", "", "", "", "", "";
  205. };
  206. &gpio3 {
  207. gpio-line-names =
  208. "", "", "", "", "", "", "", "",
  209. "", "", "", "", "", "", "", "",
  210. "", "", "", "ECSPI1_SS1", "", "USB_EXT1_OC", "USB_EXT1_PWR", "",
  211. "", "", "", "", "", "", "", "";
  212. };
  213. &gpio4 {
  214. gpio-line-names =
  215. "", "", "", "", "", "", "", "",
  216. "", "", "", "", "", "", "", "",
  217. "", "", "", "", "", "", "", "",
  218. "", "", "ETH_RESET", "", "", "BUZZER", "ETH_INTRP", "";
  219. };
  220. &gpio5 {
  221. gpio-line-names =
  222. "", "", "", "", "", "", "", "",
  223. "", "", "I2C_EN13", "I2C_EN24", "", "", "", "",
  224. "", "", "", "", "", "AUDIO_RESET", "", "",
  225. "", "", "", "", "", "", "", "";
  226. };
  227. &hdmi {
  228. pinctrl-names = "default";
  229. pinctrl-0 = <&pinctrl_hdmi>;
  230. ddc-i2c-bus = <&i2c1>;
  231. status = "okay";
  232. };
  233. /* DDC */
  234. &i2c1 {
  235. clock-frequency = <100000>;
  236. pinctrl-names = "default";
  237. pinctrl-0 = <&pinctrl_i2c1>;
  238. status = "okay";
  239. sgtl5000: audio-codec@a {
  240. compatible = "fsl,sgtl5000";
  241. reg = <0xa>;
  242. #sound-dai-cells = <0>;
  243. clocks = <&clks 201>;
  244. VDDA-supply = <&reg_3v3>;
  245. VDDIO-supply = <&reg_3v3>;
  246. VDDD-supply = <&reg_1v8>;
  247. };
  248. /* additional i2c devices are added automatically by the boot loader */
  249. };
  250. &i2c2 {
  251. clock-frequency = <50000>;
  252. pinctrl-names = "default";
  253. pinctrl-0 = <&pinctrl_i2c2>;
  254. status = "okay";
  255. /* external interface, device are configured from user space */
  256. };
  257. &i2c3 {
  258. clock-frequency = <100000>;
  259. pinctrl-names = "default";
  260. pinctrl-0 = <&pinctrl_i2c3>;
  261. status = "okay";
  262. rtc@51 {
  263. compatible = "nxp,pcf8563";
  264. reg = <0x51>;
  265. };
  266. temperature-sensor@70 {
  267. compatible = "ti,tmp103";
  268. reg = <0x70>;
  269. };
  270. };
  271. &i2c4 {
  272. clock-frequency = <50000>;
  273. pinctrl-names = "default";
  274. pinctrl-0 = <&pinctrl_i2c4>;
  275. status = "okay";
  276. };
  277. &pwm1 {
  278. pinctrl-names = "default";
  279. pinctrl-0 = <&pinctrl_pwm1>;
  280. status = "okay";
  281. };
  282. &ssi1 {
  283. #sound-dai-cells = <0>;
  284. fsl,mode = "ac97-slave";
  285. status = "okay";
  286. };
  287. &uart2 {
  288. pinctrl-names = "default";
  289. pinctrl-0 = <&pinctrl_uart2>;
  290. status = "okay";
  291. };
  292. &uart4 {
  293. pinctrl-names = "default";
  294. pinctrl-0 = <&pinctrl_uart4>;
  295. status = "okay";
  296. };
  297. &uart5 {
  298. pinctrl-names = "default";
  299. pinctrl-0 = <&pinctrl_uart5>;
  300. status = "okay";
  301. };
  302. &usbh1 {
  303. vbus-supply = <&reg_h1_vbus>;
  304. pinctrl-names = "default";
  305. pinctrl-0 = <&pinctrl_usbh1>;
  306. phy_type = "utmi";
  307. dr_mode = "host";
  308. status = "okay";
  309. };
  310. &usbotg {
  311. vbus-supply = <&reg_otg_vbus>;
  312. pinctrl-names = "default";
  313. pinctrl-0 = <&pinctrl_usbotg>;
  314. phy_type = "utmi";
  315. dr_mode = "host";
  316. status = "okay";
  317. };
  318. &usdhc1 {
  319. pinctrl-names = "default";
  320. pinctrl-0 = <&pinctrl_usdhc1>;
  321. cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
  322. no-1-8-v;
  323. disable-wp;
  324. cap-sd-highspeed;
  325. no-mmc;
  326. no-sdio;
  327. status = "okay";
  328. };
  329. &usdhc3 {
  330. pinctrl-names = "default";
  331. pinctrl-0 = <&pinctrl_usdhc3>;
  332. bus-width = <8>;
  333. no-1-8-v;
  334. non-removable;
  335. no-sd;
  336. no-sdio;
  337. status = "okay";
  338. };
  339. &iomuxc {
  340. pinctrl_audmux: audmuxgrp {
  341. fsl,pins = <
  342. MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0
  343. MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
  344. MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
  345. MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
  346. MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
  347. >;
  348. };
  349. pinctrl_can1: can1grp {
  350. fsl,pins = <
  351. MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000
  352. MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008
  353. >;
  354. };
  355. pinctrl_ecspi1: ecspi1grp {
  356. fsl,pins = <
  357. MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x1b000
  358. MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x3008
  359. MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x3008
  360. /* CS */
  361. MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x3008
  362. >;
  363. };
  364. pinctrl_enet: enetgrp {
  365. fsl,pins = <
  366. /* MX6QDL_ENET_PINGRP4 */
  367. MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
  368. MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
  369. MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
  370. MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
  371. MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
  372. MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
  373. MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
  374. MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
  375. MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
  376. MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0
  377. /* Phy reset */
  378. MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0
  379. /* nINTRP */
  380. MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0
  381. >;
  382. };
  383. pinctrl_hdmi: hdmigrp {
  384. fsl,pins = <
  385. /* NOTE: DDC is done via I2C2, so DON'T configure DDC
  386. * pins for HDMI!
  387. */
  388. MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
  389. >;
  390. };
  391. pinctrl_i2c1: i2c1grp {
  392. fsl,pins = <
  393. MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1
  394. MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1
  395. >;
  396. };
  397. pinctrl_i2c2: i2c2grp {
  398. fsl,pins = <
  399. MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
  400. MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  401. >;
  402. };
  403. pinctrl_i2c3: i2c3grp {
  404. fsl,pins = <
  405. MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
  406. MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
  407. >;
  408. };
  409. pinctrl_i2c4: i2c4grp {
  410. fsl,pins = <
  411. MX6QDL_PAD_NANDF_CS3__I2C4_SDA 0x4001f8b1
  412. MX6QDL_PAD_NANDF_WP_B__I2C4_SCL 0x4001f8b1
  413. >;
  414. };
  415. pinctrl_i2cmux: i2cmuxgrp {
  416. fsl,pins = <
  417. MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0b0
  418. MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b0b0
  419. >;
  420. };
  421. pinctrl_leds: ledsgrp {
  422. fsl,pins = <
  423. MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0
  424. MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
  425. >;
  426. };
  427. pinctrl_pwm1: pwm1grp {
  428. fsl,pins = <
  429. MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x8
  430. >;
  431. };
  432. pinctrl_uart2: uart2grp {
  433. fsl,pins = <
  434. MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
  435. MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
  436. >;
  437. };
  438. pinctrl_uart4: uart4grp {
  439. fsl,pins = <
  440. MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
  441. MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
  442. >;
  443. };
  444. pinctrl_uart5: uart5grp {
  445. fsl,pins = <
  446. MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
  447. MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
  448. >;
  449. };
  450. pinctrl_usbh1: usbh1grp {
  451. fsl,pins = <
  452. MX6QDL_PAD_GPIO_3__USB_H1_OC 0x1B058
  453. MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1B058
  454. >;
  455. };
  456. pinctrl_usbotg: usbotggrp {
  457. fsl,pins = <
  458. MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0
  459. MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
  460. >;
  461. };
  462. pinctrl_usdhc1: usdhc1grp {
  463. fsl,pins = <
  464. MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9
  465. MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9
  466. MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
  467. MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
  468. MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
  469. MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
  470. MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0
  471. >;
  472. };
  473. pinctrl_usdhc3: usdhc3grp {
  474. fsl,pins = <
  475. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099
  476. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099
  477. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099
  478. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099
  479. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099
  480. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099
  481. MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099
  482. MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099
  483. MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099
  484. MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099
  485. MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1
  486. >;
  487. };
  488. };