imx53-tqma53.dtsi 6.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright 2012 Sascha Hauer <[email protected]>, Pengutronix
  4. * Copyright 2012 Steffen Trumtrar <[email protected]>, Pengutronix
  5. */
  6. #include "imx53.dtsi"
  7. / {
  8. model = "TQ TQMa53";
  9. compatible = "tq,tqma53", "fsl,imx53";
  10. memory@70000000 {
  11. device_type = "memory";
  12. reg = <0x70000000 0x40000000>; /* Up to 1GiB */
  13. };
  14. regulators {
  15. compatible = "simple-bus";
  16. #address-cells = <1>;
  17. #size-cells = <0>;
  18. reg_3p3v: regulator@0 {
  19. compatible = "regulator-fixed";
  20. reg = <0>;
  21. regulator-name = "3P3V";
  22. regulator-min-microvolt = <3300000>;
  23. regulator-max-microvolt = <3300000>;
  24. regulator-always-on;
  25. };
  26. };
  27. };
  28. &esdhc2 {
  29. pinctrl-names = "default";
  30. pinctrl-0 = <&pinctrl_esdhc2>,
  31. <&pinctrl_esdhc2_cdwp>;
  32. vmmc-supply = <&reg_3p3v>;
  33. wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
  34. cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
  35. status = "disabled";
  36. };
  37. &uart3 {
  38. pinctrl-names = "default";
  39. pinctrl-0 = <&pinctrl_uart3>;
  40. status = "disabled";
  41. };
  42. &ecspi1 {
  43. pinctrl-names = "default";
  44. pinctrl-0 = <&pinctrl_ecspi1>;
  45. cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio3 19 GPIO_ACTIVE_LOW>,
  46. <&gpio3 24 GPIO_ACTIVE_LOW>, <&gpio3 25 GPIO_ACTIVE_LOW>;
  47. status = "disabled";
  48. };
  49. &esdhc3 { /* EMMC */
  50. pinctrl-names = "default";
  51. pinctrl-0 = <&pinctrl_esdhc3>;
  52. vmmc-supply = <&reg_3p3v>;
  53. non-removable;
  54. bus-width = <8>;
  55. status = "okay";
  56. };
  57. &iomuxc {
  58. pinctrl-names = "default";
  59. pinctrl-0 = <&pinctrl_hog>;
  60. imx53-tqma53 {
  61. pinctrl_hog: hoggrp {
  62. fsl,pins = <
  63. MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 /* SSI_MCLK */
  64. MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000 /* LCD_BLT_EN */
  65. MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000 /* LCD_RESET */
  66. MX53_PAD_PATA_DATA5__GPIO2_5 0x80000000 /* LCD_POWER */
  67. MX53_PAD_PATA_DATA6__GPIO2_6 0x80000000 /* PMIC_INT */
  68. MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 /* CSI_RST */
  69. MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 /* CSI_PWDN */
  70. MX53_PAD_GPIO_19__GPIO4_5 0x80000000 /* #SYSTEM_DOWN */
  71. MX53_PAD_GPIO_3__GPIO1_3 0x80000000
  72. MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 /* #PHY_RESET */
  73. MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000 /* LCD_CONTRAST */
  74. >;
  75. };
  76. pinctrl_audmux: audmuxgrp {
  77. fsl,pins = <
  78. MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
  79. MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
  80. MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
  81. MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
  82. >;
  83. };
  84. pinctrl_can1: can1grp {
  85. fsl,pins = <
  86. MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000
  87. MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000
  88. >;
  89. };
  90. pinctrl_can2: can2grp {
  91. fsl,pins = <
  92. MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
  93. MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
  94. >;
  95. };
  96. pinctrl_cspi: cspigrp {
  97. fsl,pins = <
  98. MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5
  99. MX53_PAD_SD1_CMD__CSPI_MOSI 0x1d5
  100. MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5
  101. >;
  102. };
  103. pinctrl_ecspi1: ecspi1grp {
  104. fsl,pins = <
  105. MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
  106. MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
  107. MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
  108. >;
  109. };
  110. pinctrl_esdhc2: esdhc2grp {
  111. fsl,pins = <
  112. MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
  113. MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
  114. MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
  115. MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
  116. MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
  117. MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
  118. >;
  119. };
  120. pinctrl_esdhc2_cdwp: esdhc2cdwp {
  121. fsl,pins = <
  122. MX53_PAD_GPIO_4__GPIO1_4 0x80000000 /* SD2_CD */
  123. MX53_PAD_GPIO_2__GPIO1_2 0x80000000 /* SD2_WP */
  124. >;
  125. };
  126. pinctrl_esdhc3: esdhc3grp {
  127. fsl,pins = <
  128. MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
  129. MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
  130. MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
  131. MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
  132. MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
  133. MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
  134. MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
  135. MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
  136. MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
  137. MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
  138. >;
  139. };
  140. pinctrl_fec: fecgrp {
  141. fsl,pins = <
  142. MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
  143. MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
  144. MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
  145. MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
  146. MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
  147. MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
  148. MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
  149. MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
  150. MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
  151. MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
  152. >;
  153. };
  154. pinctrl_i2c2: i2c2grp {
  155. fsl,pins = <
  156. MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
  157. MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
  158. >;
  159. };
  160. pinctrl_i2c3: i2c3grp {
  161. fsl,pins = <
  162. MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
  163. MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
  164. >;
  165. };
  166. pinctrl_uart1: uart1grp {
  167. fsl,pins = <
  168. MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
  169. MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
  170. >;
  171. };
  172. pinctrl_uart2: uart2grp {
  173. fsl,pins = <
  174. MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
  175. MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
  176. >;
  177. };
  178. pinctrl_uart3: uart3grp {
  179. fsl,pins = <
  180. MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
  181. MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
  182. >;
  183. };
  184. };
  185. };
  186. &pwm1 {
  187. #pwm-cells = <2>;
  188. };
  189. &pwm2 {
  190. #pwm-cells = <2>;
  191. };
  192. &uart1 {
  193. pinctrl-names = "default";
  194. pinctrl-0 = <&pinctrl_uart1>;
  195. uart-has-rtscts;
  196. status = "disabled";
  197. };
  198. &uart2 {
  199. pinctrl-names = "default";
  200. pinctrl-0 = <&pinctrl_uart2>;
  201. status = "disabled";
  202. };
  203. &can1 {
  204. pinctrl-names = "default";
  205. pinctrl-0 = <&pinctrl_can1>;
  206. status = "disabled";
  207. };
  208. &can2 {
  209. pinctrl-names = "default";
  210. pinctrl-0 = <&pinctrl_can2>;
  211. status = "disabled";
  212. };
  213. &i2c3 {
  214. pinctrl-names = "default";
  215. pinctrl-0 = <&pinctrl_i2c3>;
  216. status = "disabled";
  217. };
  218. &cspi {
  219. pinctrl-names = "default";
  220. pinctrl-0 = <&pinctrl_cspi>;
  221. cs-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>, <&gpio1 19 GPIO_ACTIVE_LOW>,
  222. <&gpio1 21 GPIO_ACTIVE_LOW>;
  223. status = "disabled";
  224. };
  225. &i2c2 {
  226. pinctrl-names = "default";
  227. pinctrl-0 = <&pinctrl_i2c2>;
  228. status = "okay";
  229. pmic: mc34708@8 {
  230. compatible = "fsl,mc34708";
  231. reg = <0x8>;
  232. fsl,mc13xxx-uses-rtc;
  233. interrupt-parent = <&gpio2>;
  234. interrupts = <6 4>; /* PATA_DATA6, active high */
  235. };
  236. sensor1: lm75@48 {
  237. compatible = "lm75";
  238. reg = <0x48>;
  239. };
  240. eeprom: 24c64@50 {
  241. compatible = "atmel,24c64";
  242. pagesize = <32>;
  243. reg = <0x50>;
  244. };
  245. };
  246. &fec {
  247. pinctrl-names = "default";
  248. pinctrl-0 = <&pinctrl_fec>;
  249. phy-mode = "rmii";
  250. status = "disabled";
  251. };