imx53-smd.dts 7.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. //
  3. // Copyright 2011 Freescale Semiconductor, Inc.
  4. // Copyright 2011 Linaro Ltd.
  5. /dts-v1/;
  6. #include <dt-bindings/input/input.h>
  7. #include "imx53.dtsi"
  8. / {
  9. model = "Freescale i.MX53 Smart Mobile Reference Design Board";
  10. compatible = "fsl,imx53-smd", "fsl,imx53";
  11. memory@70000000 {
  12. device_type = "memory";
  13. reg = <0x70000000 0x40000000>;
  14. };
  15. gpio-keys {
  16. compatible = "gpio-keys";
  17. key-volume-up {
  18. label = "Volume Up";
  19. gpios = <&gpio2 14 0>;
  20. linux,code = <KEY_VOLUMEUP>;
  21. };
  22. key-volume-down {
  23. label = "Volume Down";
  24. gpios = <&gpio2 15 0>;
  25. linux,code = <KEY_VOLUMEDOWN>;
  26. };
  27. };
  28. };
  29. &esdhc1 {
  30. pinctrl-names = "default";
  31. pinctrl-0 = <&pinctrl_esdhc1>;
  32. cd-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
  33. wp-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
  34. status = "okay";
  35. };
  36. &esdhc2 {
  37. pinctrl-names = "default";
  38. pinctrl-0 = <&pinctrl_esdhc2>;
  39. non-removable;
  40. status = "okay";
  41. };
  42. &uart3 {
  43. pinctrl-names = "default";
  44. pinctrl-0 = <&pinctrl_uart3>;
  45. uart-has-rtscts;
  46. status = "okay";
  47. };
  48. &ecspi1 {
  49. pinctrl-names = "default";
  50. pinctrl-0 = <&pinctrl_ecspi1>;
  51. cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio3 19 GPIO_ACTIVE_LOW>;
  52. status = "okay";
  53. zigbee: mc1323@0 {
  54. compatible = "fsl,mc1323";
  55. spi-max-frequency = <8000000>;
  56. reg = <0>;
  57. };
  58. flash: m25p32@1 {
  59. #address-cells = <1>;
  60. #size-cells = <1>;
  61. compatible = "st,m25p32", "st,m25p", "jedec,spi-nor";
  62. spi-max-frequency = <20000000>;
  63. reg = <1>;
  64. partition@0 {
  65. label = "U-Boot";
  66. reg = <0x0 0x40000>;
  67. read-only;
  68. };
  69. partition@40000 {
  70. label = "Kernel";
  71. reg = <0x40000 0x3c0000>;
  72. };
  73. };
  74. };
  75. &esdhc3 {
  76. pinctrl-names = "default";
  77. pinctrl-0 = <&pinctrl_esdhc3>;
  78. non-removable;
  79. status = "okay";
  80. };
  81. &iomuxc {
  82. pinctrl-names = "default";
  83. pinctrl-0 = <&pinctrl_hog>;
  84. imx53-smd {
  85. pinctrl_hog: hoggrp {
  86. fsl,pins = <
  87. MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000
  88. MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000
  89. MX53_PAD_EIM_EB2__GPIO2_30 0x80000000
  90. MX53_PAD_EIM_DA13__GPIO3_13 0x80000000
  91. MX53_PAD_EIM_D19__GPIO3_19 0x80000000
  92. MX53_PAD_KEY_ROW2__GPIO4_11 0x80000000
  93. MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
  94. >;
  95. };
  96. pinctrl_ecspi1: ecspi1grp {
  97. fsl,pins = <
  98. MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
  99. MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
  100. MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
  101. >;
  102. };
  103. pinctrl_esdhc1: esdhc1grp {
  104. fsl,pins = <
  105. MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
  106. MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
  107. MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
  108. MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
  109. MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
  110. MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
  111. >;
  112. };
  113. pinctrl_esdhc2: esdhc2grp {
  114. fsl,pins = <
  115. MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
  116. MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
  117. MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
  118. MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
  119. MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
  120. MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
  121. >;
  122. };
  123. pinctrl_esdhc3: esdhc3grp {
  124. fsl,pins = <
  125. MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
  126. MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
  127. MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
  128. MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
  129. MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
  130. MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
  131. MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
  132. MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
  133. MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
  134. MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
  135. >;
  136. };
  137. pinctrl_fec: fecgrp {
  138. fsl,pins = <
  139. MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
  140. MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
  141. MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
  142. MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
  143. MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
  144. MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
  145. MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
  146. MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
  147. MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
  148. MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
  149. >;
  150. };
  151. pinctrl_i2c1: i2c1grp {
  152. fsl,pins = <
  153. MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000
  154. MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000
  155. >;
  156. };
  157. pinctrl_i2c2: i2c2grp {
  158. fsl,pins = <
  159. MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
  160. MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
  161. >;
  162. };
  163. pinctrl_ipu_csi0: ipucsi0grp {
  164. fsl,pins = <
  165. MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1c4
  166. MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1c4
  167. MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1c4
  168. MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1c4
  169. MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1c4
  170. MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1c4
  171. MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1c4
  172. MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1c4
  173. MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1e4
  174. MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1e4
  175. MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1e4
  176. MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x1e4
  177. >;
  178. };
  179. pinctrl_ov5642: ov5642grp {
  180. fsl,pins = <
  181. MX53_PAD_NANDF_WP_B__GPIO6_9 0x1e4
  182. MX53_PAD_NANDF_RB0__GPIO6_10 0x1e4
  183. MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x1c4
  184. >;
  185. };
  186. pinctrl_uart1: uart1grp {
  187. fsl,pins = <
  188. MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4
  189. MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4
  190. >;
  191. };
  192. pinctrl_uart2: uart2grp {
  193. fsl,pins = <
  194. MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
  195. MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
  196. >;
  197. };
  198. pinctrl_uart3: uart3grp {
  199. fsl,pins = <
  200. MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
  201. MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
  202. MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4
  203. MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4
  204. >;
  205. };
  206. };
  207. };
  208. &uart1 {
  209. pinctrl-names = "default";
  210. pinctrl-0 = <&pinctrl_uart1>;
  211. status = "okay";
  212. };
  213. &uart2 {
  214. pinctrl-names = "default";
  215. pinctrl-0 = <&pinctrl_uart2>;
  216. status = "okay";
  217. };
  218. &i2c2 {
  219. pinctrl-names = "default";
  220. pinctrl-0 = <&pinctrl_i2c2>;
  221. status = "okay";
  222. codec: sgtl5000@a {
  223. compatible = "fsl,sgtl5000";
  224. reg = <0x0a>;
  225. };
  226. magnetometer: mag3110@e {
  227. compatible = "fsl,mag3110";
  228. reg = <0x0e>;
  229. };
  230. touchkey: mpr121@5a {
  231. compatible = "fsl,mpr121";
  232. reg = <0x5a>;
  233. };
  234. };
  235. &i2c1 {
  236. pinctrl-names = "default";
  237. pinctrl-0 = <&pinctrl_i2c1>;
  238. status = "okay";
  239. accelerometer: mma8450@1c {
  240. compatible = "fsl,mma8450";
  241. reg = <0x1c>;
  242. };
  243. camera: ov5642@3c {
  244. compatible = "ovti,ov5642";
  245. reg = <0x3c>;
  246. pinctrl-names = "default";
  247. pinctrl-0 = <&pinctrl_ov5642>;
  248. assigned-clocks = <&clks IMX5_CLK_SSI_EXT1_SEL>,
  249. <&clks IMX5_CLK_SSI_EXT1_COM_SEL>;
  250. assigned-clock-parents = <&clks IMX5_CLK_PLL2_SW>,
  251. <&clks IMX5_CLK_SSI_EXT1_PODF>;
  252. assigned-clock-rates = <0>, <24000000>;
  253. clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>;
  254. clock-names = "xclk";
  255. DVDD-supply = <&ldo9_reg>;
  256. AVDD-supply = <&ldo7_reg>;
  257. reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>;
  258. powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>;
  259. port {
  260. ov5642_to_ipu_csi0: endpoint {
  261. remote-endpoint = <&ipu_csi0_from_parallel_sensor>;
  262. bus-width = <8>;
  263. hsync-active = <1>;
  264. vsync-active = <1>;
  265. };
  266. };
  267. };
  268. pmic: dialog@48 {
  269. compatible = "dlg,da9053", "dlg,da9052";
  270. reg = <0x48>;
  271. interrupt-parent = <&gpio7>;
  272. interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
  273. regulators {
  274. ldo7_reg: ldo7 {
  275. regulator-min-microvolt = <1200000>;
  276. regulator-max-microvolt = <3600000>;
  277. };
  278. ldo9_reg: ldo9 {
  279. regulator-min-microvolt = <1250000>;
  280. regulator-max-microvolt = <3650000>;
  281. };
  282. };
  283. };
  284. };
  285. &fec {
  286. pinctrl-names = "default";
  287. pinctrl-0 = <&pinctrl_fec>;
  288. phy-mode = "rmii";
  289. phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
  290. status = "okay";
  291. };
  292. &ipu_csi0_from_parallel_sensor {
  293. remote-endpoint = <&ov5642_to_ipu_csi0>;
  294. data-shift = <12>; /* Lines 19:12 used */
  295. hsync-active = <1>;
  296. vsync-active = <1>;
  297. };
  298. &ipu_csi0 {
  299. pinctrl-names = "default";
  300. pinctrl-0 = <&pinctrl_ipu_csi0>;
  301. };