imx53-mba53.dts 5.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright 2012 Sascha Hauer <[email protected]>, Pengutronix
  4. * Copyright 2012 Steffen Trumtrar <[email protected]>, Pengutronix
  5. */
  6. /dts-v1/;
  7. #include "imx53-tqma53.dtsi"
  8. / {
  9. model = "TQ MBa53 starter kit";
  10. compatible = "tq,mba53", "tq,tqma53", "fsl,imx53";
  11. chosen {
  12. stdout-path = &uart2;
  13. };
  14. backlight {
  15. compatible = "pwm-backlight";
  16. pwms = <&pwm2 0 50000>;
  17. brightness-levels = <0 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100>;
  18. default-brightness-level = <10>;
  19. enable-gpios = <&gpio7 7 0>;
  20. power-supply = <&reg_backlight>;
  21. };
  22. disp1: disp1 {
  23. compatible = "fsl,imx-parallel-display";
  24. pinctrl-names = "default";
  25. pinctrl-0 = <&pinctrl_disp1_1>;
  26. interface-pix-fmt = "rgb24";
  27. status = "disabled";
  28. port {
  29. display1_in: endpoint {
  30. remote-endpoint = <&ipu_di1_disp1>;
  31. };
  32. };
  33. };
  34. regulators {
  35. compatible = "simple-bus";
  36. #address-cells = <1>;
  37. #size-cells = <0>;
  38. reg_backlight: regulator@0 {
  39. compatible = "regulator-fixed";
  40. reg = <0>;
  41. regulator-name = "lcd-supply";
  42. gpio = <&gpio2 5 0>;
  43. startup-delay-us = <5000>;
  44. };
  45. reg_3p2v: regulator@1 {
  46. compatible = "regulator-fixed";
  47. reg = <1>;
  48. regulator-name = "3P2V";
  49. regulator-min-microvolt = <3200000>;
  50. regulator-max-microvolt = <3200000>;
  51. regulator-always-on;
  52. };
  53. };
  54. sound {
  55. compatible = "tq,imx53-mba53-sgtl5000",
  56. "fsl,imx-audio-sgtl5000";
  57. model = "imx53-mba53-sgtl5000";
  58. ssi-controller = <&ssi2>;
  59. audio-codec = <&codec>;
  60. audio-routing =
  61. "MIC_IN", "Mic Jack",
  62. "Mic Jack", "Mic Bias",
  63. "Headphone Jack", "HP_OUT";
  64. mux-int-port = <2>;
  65. mux-ext-port = <5>;
  66. };
  67. };
  68. &ldb {
  69. pinctrl-names = "default";
  70. pinctrl-0 = <&pinctrl_lvds1_1>;
  71. status = "disabled";
  72. };
  73. &iomuxc {
  74. lvds1 {
  75. pinctrl_lvds1_1: lvds1-grp1 {
  76. fsl,pins = <
  77. MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
  78. MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
  79. MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
  80. MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
  81. MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
  82. >;
  83. };
  84. pinctrl_lvds1_2: lvds1-grp2 {
  85. fsl,pins = <
  86. MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000
  87. MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000
  88. MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000
  89. MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000
  90. MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000
  91. >;
  92. };
  93. };
  94. disp1 {
  95. pinctrl_disp1_1: disp1-grp1 {
  96. fsl,pins = <
  97. MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x80000000 /* DISP1_CLK */
  98. MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x80000000 /* DISP1_DRDY */
  99. MX53_PAD_EIM_D23__IPU_DI1_PIN2 0x80000000 /* DISP1_HSYNC */
  100. MX53_PAD_EIM_EB3__IPU_DI1_PIN3 0x80000000 /* DISP1_VSYNC */
  101. MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x80000000
  102. MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x80000000
  103. MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x80000000
  104. MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x80000000
  105. MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x80000000
  106. MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x80000000
  107. MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x80000000
  108. MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x80000000
  109. MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x80000000
  110. MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x80000000
  111. MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x80000000
  112. MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x80000000
  113. MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x80000000
  114. MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x80000000
  115. MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x80000000
  116. MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x80000000
  117. MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x80000000
  118. MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x80000000
  119. MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x80000000
  120. MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x80000000
  121. MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x80000000
  122. MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x80000000
  123. MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x80000000
  124. MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x80000000
  125. >;
  126. };
  127. };
  128. tve {
  129. pinctrl_vga_sync_1: vgasync-grp1 {
  130. fsl,pins = <
  131. /* VGA_VSYNC, HSYNC with max drive strength */
  132. MX53_PAD_EIM_CS1__IPU_DI1_PIN6 0xe6
  133. MX53_PAD_EIM_DA15__IPU_DI1_PIN4 0xe6
  134. >;
  135. };
  136. };
  137. };
  138. &ipu_di1_disp1 {
  139. remote-endpoint = <&display1_in>;
  140. };
  141. &cspi {
  142. status = "okay";
  143. };
  144. &audmux {
  145. status = "okay";
  146. pinctrl-names = "default";
  147. pinctrl-0 = <&pinctrl_audmux>;
  148. };
  149. &i2c2 {
  150. codec: sgtl5000@a {
  151. compatible = "fsl,sgtl5000";
  152. reg = <0x0a>;
  153. clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>;
  154. VDDA-supply = <&reg_3p2v>;
  155. VDDIO-supply = <&reg_3p2v>;
  156. };
  157. expander: pca9554@20 {
  158. compatible = "pca9554";
  159. reg = <0x20>;
  160. interrupts = <109>;
  161. #gpio-cells = <2>;
  162. gpio-controller;
  163. };
  164. sensor2: lm75@49 {
  165. compatible = "lm75";
  166. reg = <0x49>;
  167. };
  168. };
  169. &fec {
  170. phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
  171. status = "okay";
  172. };
  173. &esdhc2 {
  174. status = "okay";
  175. };
  176. &uart3 {
  177. status = "okay";
  178. };
  179. &ecspi1 {
  180. status = "okay";
  181. };
  182. &usbotg {
  183. dr_mode = "host";
  184. status = "okay";
  185. };
  186. &usbh1 {
  187. status = "okay";
  188. };
  189. &uart1 {
  190. status = "okay";
  191. };
  192. &ssi2 {
  193. status = "okay";
  194. };
  195. &uart2 {
  196. status = "okay";
  197. };
  198. &can1 {
  199. status = "okay";
  200. };
  201. &can2 {
  202. status = "okay";
  203. };
  204. &i2c3 {
  205. status = "okay";
  206. };
  207. &tve {
  208. pinctrl-names = "default";
  209. pinctrl-0 = <&pinctrl_vga_sync_1>;
  210. ddc-i2c-bus = <&i2c3>;
  211. fsl,tve-mode = "vga";
  212. fsl,hsync-pin = <4>;
  213. fsl,vsync-pin = <6>;
  214. status = "okay";
  215. };