imx51-zii-scu2-mezz.dts 8.8 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /*
  3. * Copyright (C) 2018 Zodiac Inflight Innovations
  4. */
  5. /dts-v1/;
  6. #include "imx51.dtsi"
  7. / {
  8. model = "ZII SCU2 Mezz Board";
  9. compatible = "zii,imx51-scu2-mezz", "fsl,imx51";
  10. chosen {
  11. stdout-path = &uart1;
  12. };
  13. /* Will be filled by the bootloader */
  14. memory@90000000 {
  15. device_type = "memory";
  16. reg = <0x90000000 0>;
  17. };
  18. aliases {
  19. mdio-gpio0 = &mdio_gpio;
  20. };
  21. usb_vbus: regulator-usb-vbus {
  22. compatible = "regulator-fixed";
  23. pinctrl-names = "default";
  24. pinctrl-0 = <&pinctrl_usb_mmc_reset>;
  25. gpio = <&gpio3 13 GPIO_ACTIVE_LOW>;
  26. startup-delay-us = <150000>;
  27. regulator-name = "usb_vbus";
  28. regulator-min-microvolt = <5000000>;
  29. regulator-max-microvolt = <5000000>;
  30. };
  31. mdio_gpio: mdio-gpio {
  32. compatible = "virtual,mdio-gpio";
  33. pinctrl-names = "default";
  34. pinctrl-0 = <&pinctrl_swmdio>;
  35. gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>, /* mdc */
  36. <&gpio2 6 GPIO_ACTIVE_HIGH>; /* mdio */
  37. #address-cells = <1>;
  38. #size-cells = <0>;
  39. switch@0 {
  40. compatible = "marvell,mv88e6085";
  41. reg = <0>;
  42. dsa,member = <0 0>;
  43. eeprom-length = <512>;
  44. interrupt-parent = <&gpio1>;
  45. interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
  46. interrupt-controller;
  47. #interrupt-cells = <2>;
  48. ports {
  49. #address-cells = <1>;
  50. #size-cells = <0>;
  51. port@0 {
  52. reg = <0>;
  53. label = "port4";
  54. };
  55. port@1 {
  56. reg = <1>;
  57. label = "port5";
  58. };
  59. port@2 {
  60. reg = <2>;
  61. label = "port6";
  62. };
  63. port@3 {
  64. reg = <3>;
  65. label = "port7";
  66. };
  67. port@4 {
  68. reg = <4>;
  69. label = "cpu";
  70. ethernet = <&fec>;
  71. fixed-link {
  72. speed = <100>;
  73. full-duplex;
  74. };
  75. };
  76. port@5 {
  77. reg = <5>;
  78. label = "mezz2esb";
  79. phy-mode = "sgmii";
  80. fixed-link {
  81. speed = <1000>;
  82. full-duplex;
  83. };
  84. };
  85. };
  86. };
  87. };
  88. };
  89. &cpu {
  90. cpu-supply = <&sw1_reg>;
  91. };
  92. &ecspi1 {
  93. pinctrl-names = "default";
  94. pinctrl-0 = <&pinctrl_ecspi1>;
  95. cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
  96. <&gpio4 25 GPIO_ACTIVE_LOW>;
  97. status = "okay";
  98. pmic@0 {
  99. compatible = "fsl,mc13892";
  100. pinctrl-names = "default";
  101. pinctrl-0 = <&pinctrl_pmic>;
  102. spi-max-frequency = <6000000>;
  103. spi-cs-high;
  104. reg = <0>;
  105. interrupt-parent = <&gpio1>;
  106. interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
  107. fsl,mc13xxx-uses-adc;
  108. regulators {
  109. sw1_reg: sw1 {
  110. regulator-min-microvolt = <600000>;
  111. regulator-max-microvolt = <1375000>;
  112. regulator-boot-on;
  113. regulator-always-on;
  114. };
  115. sw2_reg: sw2 {
  116. regulator-min-microvolt = <900000>;
  117. regulator-max-microvolt = <1850000>;
  118. regulator-boot-on;
  119. regulator-always-on;
  120. };
  121. sw3_reg: sw3 {
  122. regulator-min-microvolt = <1100000>;
  123. regulator-max-microvolt = <1850000>;
  124. regulator-boot-on;
  125. regulator-always-on;
  126. };
  127. sw4_reg: sw4 {
  128. regulator-min-microvolt = <1100000>;
  129. regulator-max-microvolt = <1850000>;
  130. regulator-boot-on;
  131. regulator-always-on;
  132. };
  133. vpll_reg: vpll {
  134. regulator-min-microvolt = <1050000>;
  135. regulator-max-microvolt = <1800000>;
  136. regulator-boot-on;
  137. regulator-always-on;
  138. };
  139. vdig_reg: vdig {
  140. regulator-min-microvolt = <1650000>;
  141. regulator-max-microvolt = <1650000>;
  142. regulator-boot-on;
  143. };
  144. vsd_reg: vsd {
  145. regulator-min-microvolt = <1800000>;
  146. regulator-max-microvolt = <3150000>;
  147. regulator-always-on;
  148. };
  149. vusb_reg: vusb {
  150. regulator-always-on;
  151. };
  152. vusb2_reg: vusb2 {
  153. regulator-min-microvolt = <2400000>;
  154. regulator-max-microvolt = <2775000>;
  155. regulator-boot-on;
  156. regulator-always-on;
  157. };
  158. vvideo_reg: vvideo {
  159. regulator-min-microvolt = <2775000>;
  160. regulator-max-microvolt = <2775000>;
  161. };
  162. vaudio_reg: vaudio {
  163. regulator-min-microvolt = <2300000>;
  164. regulator-max-microvolt = <3000000>;
  165. };
  166. vcam_reg: vcam {
  167. regulator-min-microvolt = <2500000>;
  168. regulator-max-microvolt = <3000000>;
  169. };
  170. vgen1_reg: vgen1 {
  171. regulator-min-microvolt = <1200000>;
  172. regulator-max-microvolt = <1200000>;
  173. };
  174. vgen2_reg: vgen2 {
  175. regulator-min-microvolt = <1200000>;
  176. regulator-max-microvolt = <3150000>;
  177. regulator-always-on;
  178. };
  179. vgen3_reg: vgen3 {
  180. regulator-min-microvolt = <1800000>;
  181. regulator-max-microvolt = <2900000>;
  182. regulator-always-on;
  183. };
  184. };
  185. leds {
  186. #address-cells = <1>;
  187. #size-cells = <0>;
  188. led-control = <0x0 0x0 0x3f83f8 0x0>;
  189. sysled3: led3@3 {
  190. reg = <3>;
  191. label = "system:red:power";
  192. linux,default-trigger = "default-on";
  193. };
  194. sysled4: led4@4 {
  195. reg = <4>;
  196. label = "system:green:act";
  197. linux,default-trigger = "heartbeat";
  198. };
  199. };
  200. };
  201. flash@1 {
  202. compatible = "atmel,at45", "atmel,dataflash";
  203. reg = <1>;
  204. spi-max-frequency = <25000000>;
  205. };
  206. };
  207. &esdhc1 {
  208. pinctrl-names = "default";
  209. pinctrl-0 = <&pinctrl_esdhc1>;
  210. bus-width = <8>;
  211. non-removable;
  212. no-1-8-v;
  213. no-sdio;
  214. no-sd;
  215. status = "okay";
  216. };
  217. &esdhc4 {
  218. pinctrl-names = "default";
  219. pinctrl-0 = <&pinctrl_esdhc4>;
  220. bus-width = <4>;
  221. no-1-8-v;
  222. no-sdio;
  223. cd-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;
  224. status = "okay";
  225. };
  226. &fec {
  227. pinctrl-names = "default";
  228. pinctrl-0 = <&pinctrl_fec>;
  229. phy-mode = "mii";
  230. status = "okay";
  231. phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
  232. phy-reset-duration = <1>;
  233. phy-supply = <&vgen3_reg>;
  234. phy-handle = <&ethphy>;
  235. mdio {
  236. #address-cells = <1>;
  237. #size-cells = <0>;
  238. ethphy: ethernet-phy@0 {
  239. reg = <0>;
  240. max-speed = <100>;
  241. };
  242. };
  243. };
  244. &i2c2 {
  245. pinctrl-names = "default";
  246. pinctrl-0 = <&pinctrl_i2c2>;
  247. status = "okay";
  248. eeprom@50 {
  249. compatible = "atmel,24c04";
  250. pagesize = <16>;
  251. reg = <0x50>;
  252. };
  253. };
  254. &uart1 {
  255. pinctrl-names = "default";
  256. pinctrl-0 = <&pinctrl_uart1>;
  257. status = "okay";
  258. };
  259. &uart3 {
  260. pinctrl-names = "default";
  261. pinctrl-0 = <&pinctrl_uart3>;
  262. status = "okay";
  263. rave-sp {
  264. compatible = "zii,rave-sp-mezz";
  265. current-speed = <57600>;
  266. #address-cells = <1>;
  267. #size-cells = <1>;
  268. watchdog {
  269. compatible = "zii,rave-sp-watchdog-legacy";
  270. };
  271. eeprom@a4 {
  272. compatible = "zii,rave-sp-eeprom";
  273. reg = <0xa4 0x4000>;
  274. #address-cells = <1>;
  275. #size-cells = <1>;
  276. zii,eeprom-name = "main-eeprom";
  277. };
  278. };
  279. };
  280. &usbotg {
  281. dr_mode = "host";
  282. disable-over-current;
  283. phy_type = "utmi_wide";
  284. vbus-supply = <&usb_vbus>;
  285. status = "okay";
  286. };
  287. &usbphy0 {
  288. vcc-supply = <&vusb2_reg>;
  289. };
  290. &vpu {
  291. status = "disabled";
  292. };
  293. &wdog1 {
  294. status = "disabled";
  295. };
  296. &iomuxc {
  297. pinctrl_ecspi1: ecspi1grp {
  298. fsl,pins = <
  299. MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
  300. MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
  301. MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
  302. MX51_PAD_CSPI1_SS0__GPIO4_24 0x85
  303. MX51_PAD_CSPI1_SS1__GPIO4_25 0x85
  304. >;
  305. };
  306. pinctrl_esdhc1: esdhc1grp {
  307. fsl,pins = <
  308. MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
  309. MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
  310. MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
  311. MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
  312. MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
  313. MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
  314. MX51_PAD_SD2_DATA0__SD1_DAT4 0x20d5
  315. MX51_PAD_SD2_DATA1__SD1_DAT5 0x20d5
  316. MX51_PAD_SD2_DATA2__SD1_DAT6 0x20d5
  317. MX51_PAD_SD2_DATA3__SD1_DAT7 0x20d5
  318. >;
  319. };
  320. pinctrl_esdhc4: esdhc4grp {
  321. fsl,pins = <
  322. MX51_PAD_NANDF_RB1__SD4_CMD 0x400020d5
  323. MX51_PAD_NANDF_CS2__SD4_CLK 0x20d5
  324. MX51_PAD_NANDF_CS3__SD4_DAT0 0x20d5
  325. MX51_PAD_NANDF_CS4__SD4_DAT1 0x20d5
  326. MX51_PAD_NANDF_CS5__SD4_DAT2 0x20d5
  327. MX51_PAD_NANDF_CS6__SD4_DAT3 0x20d5
  328. MX51_PAD_NANDF_D0__GPIO4_8 0x100
  329. >;
  330. };
  331. pinctrl_fec: fecgrp {
  332. fsl,pins = <
  333. MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x2004
  334. MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x2004
  335. MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x2004
  336. MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x2004
  337. MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x2004
  338. MX51_PAD_DISP2_DAT10__FEC_COL 0x0180
  339. MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x0180
  340. MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x20a4
  341. MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x20a4
  342. MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x2180
  343. MX51_PAD_DI_GP3__FEC_TX_ER 0x2004
  344. MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x2180
  345. MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x0085
  346. MX51_PAD_DI_GP4__FEC_RDATA2 0x0085
  347. MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x0085
  348. MX51_PAD_DI2_PIN2__FEC_MDC 0x2004
  349. MX51_PAD_DI2_PIN3__FEC_MDIO 0x01f5
  350. MX51_PAD_DI2_PIN4__FEC_CRS 0x0180
  351. MX51_PAD_EIM_A20__GPIO2_14 0x0085
  352. MX51_PAD_EIM_A21__GPIO2_15 0x00e5
  353. >;
  354. };
  355. pinctrl_i2c2: i2c2grp {
  356. fsl,pins = <
  357. MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
  358. MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
  359. >;
  360. };
  361. pinctrl_pmic: pmicgrp {
  362. fsl,pins = <
  363. MX51_PAD_GPIO1_4__GPIO1_4 0x85
  364. MX51_PAD_GPIO1_8__GPIO1_8 0xe5
  365. >;
  366. };
  367. pinctrl_swmdio: swmdiogrp {
  368. fsl,pins = <
  369. MX51_PAD_EIM_D22__GPIO2_6 0x100
  370. MX51_PAD_EIM_D23__GPIO2_7 0x100
  371. >;
  372. };
  373. pinctrl_uart1: uart1grp {
  374. fsl,pins = <
  375. MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
  376. MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
  377. >;
  378. };
  379. pinctrl_uart3: uart3grp {
  380. fsl,pins = <
  381. MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
  382. MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
  383. >;
  384. };
  385. pinctrl_usb_mmc_reset: usbmmcgrp {
  386. fsl,pins = <
  387. MX51_PAD_CSI1_D9__GPIO3_13 0x85
  388. >;
  389. };
  390. };