imx51-babbage.dts 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. //
  3. // Copyright 2011 Freescale Semiconductor, Inc.
  4. // Copyright 2011 Linaro Ltd.
  5. /dts-v1/;
  6. #include "imx51.dtsi"
  7. / {
  8. model = "Freescale i.MX51 Babbage Board";
  9. compatible = "fsl,imx51-babbage", "fsl,imx51";
  10. chosen {
  11. stdout-path = &uart1;
  12. };
  13. memory@90000000 {
  14. device_type = "memory";
  15. reg = <0x90000000 0x20000000>;
  16. };
  17. ckih1 {
  18. clock-frequency = <22579200>;
  19. };
  20. clk_osc: clk-osc {
  21. compatible = "fixed-clock";
  22. #clock-cells = <0>;
  23. clock-frequency = <26000000>;
  24. };
  25. clk_osc_gate: clk-osc-gate {
  26. compatible = "gpio-gate-clock";
  27. pinctrl-names = "default";
  28. pinctrl-0 = <&pinctrl_clk26mhz_osc>;
  29. clocks = <&clk_osc>;
  30. #clock-cells = <0>;
  31. enable-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>;
  32. };
  33. clk_audio: clk-audio {
  34. compatible = "gpio-gate-clock";
  35. pinctrl-names = "default";
  36. pinctrl-0 = <&pinctrl_clk26mhz_audio>;
  37. clocks = <&clk_osc_gate>;
  38. #clock-cells = <0>;
  39. enable-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
  40. };
  41. clk_usb: clk-usb {
  42. compatible = "gpio-gate-clock";
  43. pinctrl-names = "default";
  44. pinctrl-0 = <&pinctrl_clk26mhz_usb>;
  45. clocks = <&clk_osc_gate>;
  46. #clock-cells = <0>;
  47. enable-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
  48. };
  49. display1: disp1 {
  50. compatible = "fsl,imx-parallel-display";
  51. #address-cells = <1>;
  52. #size-cells = <0>;
  53. interface-pix-fmt = "rgb24";
  54. pinctrl-names = "default";
  55. pinctrl-0 = <&pinctrl_ipu_disp1>;
  56. port@0 {
  57. reg = <0>;
  58. display0_in: endpoint {
  59. remote-endpoint = <&ipu_di0_disp1>;
  60. };
  61. };
  62. port@1 {
  63. reg = <1>;
  64. parallel_display_out: endpoint {
  65. remote-endpoint = <&tfp410_in>;
  66. };
  67. };
  68. };
  69. display2: disp2 {
  70. compatible = "fsl,imx-parallel-display";
  71. interface-pix-fmt = "rgb565";
  72. pinctrl-names = "default";
  73. pinctrl-0 = <&pinctrl_ipu_disp2>;
  74. status = "disabled";
  75. display-timings {
  76. native-mode = <&timing1>;
  77. timing1: claawvga {
  78. clock-frequency = <27000000>;
  79. hactive = <800>;
  80. vactive = <480>;
  81. hback-porch = <40>;
  82. hfront-porch = <60>;
  83. vback-porch = <10>;
  84. vfront-porch = <10>;
  85. hsync-len = <20>;
  86. vsync-len = <10>;
  87. hsync-active = <0>;
  88. vsync-active = <0>;
  89. de-active = <1>;
  90. pixelclk-active = <0>;
  91. };
  92. };
  93. port {
  94. display1_in: endpoint {
  95. remote-endpoint = <&ipu_di1_disp2>;
  96. };
  97. };
  98. };
  99. dvi-connector {
  100. compatible = "dvi-connector";
  101. digital;
  102. port {
  103. dvi_connector_in: endpoint {
  104. remote-endpoint = <&tfp410_out>;
  105. };
  106. };
  107. };
  108. dvi-encoder {
  109. compatible = "ti,tfp410";
  110. ports {
  111. #address-cells = <1>;
  112. #size-cells = <0>;
  113. port@0 {
  114. reg = <0>;
  115. tfp410_in: endpoint {
  116. remote-endpoint = <&parallel_display_out>;
  117. };
  118. };
  119. port@1 {
  120. reg = <1>;
  121. tfp410_out: endpoint {
  122. remote-endpoint = <&dvi_connector_in>;
  123. };
  124. };
  125. };
  126. };
  127. gpio-keys {
  128. compatible = "gpio-keys";
  129. pinctrl-names = "default";
  130. pinctrl-0 = <&pinctrl_gpio_keys>;
  131. key-power {
  132. label = "Power Button";
  133. gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
  134. linux,code = <KEY_POWER>;
  135. wakeup-source;
  136. };
  137. };
  138. leds {
  139. compatible = "gpio-leds";
  140. pinctrl-names = "default";
  141. pinctrl-0 = <&pinctrl_gpio_leds>;
  142. led-diagnostic {
  143. label = "diagnostic";
  144. gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
  145. };
  146. };
  147. regulators {
  148. compatible = "simple-bus";
  149. #address-cells = <1>;
  150. #size-cells = <0>;
  151. reg_hub_reset: regulator@0 {
  152. compatible = "regulator-fixed";
  153. pinctrl-names = "default";
  154. pinctrl-0 = <&pinctrl_usbotgreg>;
  155. reg = <0>;
  156. regulator-name = "hub_reset";
  157. regulator-min-microvolt = <5000000>;
  158. regulator-max-microvolt = <5000000>;
  159. gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
  160. enable-active-high;
  161. };
  162. };
  163. sound {
  164. compatible = "fsl,imx51-babbage-sgtl5000",
  165. "fsl,imx-audio-sgtl5000";
  166. model = "imx51-babbage-sgtl5000";
  167. ssi-controller = <&ssi2>;
  168. audio-codec = <&sgtl5000>;
  169. audio-routing =
  170. "MIC_IN", "Mic Jack",
  171. "Mic Jack", "Mic Bias",
  172. "Headphone Jack", "HP_OUT";
  173. mux-int-port = <2>;
  174. mux-ext-port = <3>;
  175. };
  176. usbphy1: usbphy1 {
  177. compatible = "usb-nop-xceiv";
  178. pinctrl-names = "default";
  179. pinctrl-0 = <&pinctrl_usbh1reg>;
  180. clocks = <&clk_usb>;
  181. clock-names = "main_clk";
  182. reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
  183. vcc-supply = <&vusb_reg>;
  184. #phy-cells = <0>;
  185. };
  186. };
  187. &audmux {
  188. pinctrl-names = "default";
  189. pinctrl-0 = <&pinctrl_audmux>;
  190. status = "okay";
  191. };
  192. &ecspi1 {
  193. pinctrl-names = "default";
  194. pinctrl-0 = <&pinctrl_ecspi1>;
  195. cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
  196. <&gpio4 25 GPIO_ACTIVE_LOW>;
  197. status = "okay";
  198. pmic: mc13892@0 {
  199. compatible = "fsl,mc13892";
  200. pinctrl-names = "default";
  201. pinctrl-0 = <&pinctrl_pmic>;
  202. spi-max-frequency = <6000000>;
  203. spi-cs-high;
  204. reg = <0>;
  205. interrupt-parent = <&gpio1>;
  206. interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
  207. fsl,mc13xxx-uses-adc;
  208. fsl,mc13xxx-uses-rtc;
  209. regulators {
  210. sw1_reg: sw1 {
  211. regulator-min-microvolt = <600000>;
  212. regulator-max-microvolt = <1375000>;
  213. regulator-boot-on;
  214. regulator-always-on;
  215. };
  216. sw2_reg: sw2 {
  217. regulator-min-microvolt = <900000>;
  218. regulator-max-microvolt = <1850000>;
  219. regulator-boot-on;
  220. regulator-always-on;
  221. };
  222. sw3_reg: sw3 {
  223. regulator-min-microvolt = <1100000>;
  224. regulator-max-microvolt = <1850000>;
  225. regulator-boot-on;
  226. regulator-always-on;
  227. };
  228. sw4_reg: sw4 {
  229. regulator-min-microvolt = <1100000>;
  230. regulator-max-microvolt = <1850000>;
  231. regulator-boot-on;
  232. regulator-always-on;
  233. };
  234. vpll_reg: vpll {
  235. regulator-min-microvolt = <1050000>;
  236. regulator-max-microvolt = <1800000>;
  237. regulator-boot-on;
  238. regulator-always-on;
  239. };
  240. vdig_reg: vdig {
  241. regulator-min-microvolt = <1650000>;
  242. regulator-max-microvolt = <1650000>;
  243. regulator-boot-on;
  244. };
  245. vsd_reg: vsd {
  246. regulator-min-microvolt = <1800000>;
  247. regulator-max-microvolt = <3150000>;
  248. };
  249. vusb_reg: vusb {
  250. regulator-boot-on;
  251. };
  252. vusb2_reg: vusb2 {
  253. regulator-min-microvolt = <2400000>;
  254. regulator-max-microvolt = <2775000>;
  255. regulator-boot-on;
  256. regulator-always-on;
  257. };
  258. vvideo_reg: vvideo {
  259. regulator-min-microvolt = <2775000>;
  260. regulator-max-microvolt = <2775000>;
  261. };
  262. vaudio_reg: vaudio {
  263. regulator-min-microvolt = <2300000>;
  264. regulator-max-microvolt = <3000000>;
  265. };
  266. vcam_reg: vcam {
  267. regulator-min-microvolt = <2500000>;
  268. regulator-max-microvolt = <3000000>;
  269. };
  270. vgen1_reg: vgen1 {
  271. regulator-min-microvolt = <1200000>;
  272. regulator-max-microvolt = <1200000>;
  273. };
  274. vgen2_reg: vgen2 {
  275. regulator-min-microvolt = <1200000>;
  276. regulator-max-microvolt = <3150000>;
  277. regulator-always-on;
  278. };
  279. vgen3_reg: vgen3 {
  280. regulator-min-microvolt = <1800000>;
  281. regulator-max-microvolt = <2900000>;
  282. regulator-always-on;
  283. };
  284. };
  285. };
  286. flash: at45db321d@1 {
  287. #address-cells = <1>;
  288. #size-cells = <1>;
  289. compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
  290. spi-max-frequency = <25000000>;
  291. reg = <1>;
  292. partition@0 {
  293. label = "U-Boot";
  294. reg = <0x0 0x40000>;
  295. read-only;
  296. };
  297. partition@40000 {
  298. label = "Kernel";
  299. reg = <0x40000 0x3c0000>;
  300. };
  301. };
  302. };
  303. &esdhc1 {
  304. pinctrl-names = "default";
  305. pinctrl-0 = <&pinctrl_esdhc1>;
  306. cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
  307. wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
  308. status = "okay";
  309. };
  310. &esdhc2 {
  311. pinctrl-names = "default";
  312. pinctrl-0 = <&pinctrl_esdhc2>;
  313. cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
  314. wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
  315. status = "okay";
  316. };
  317. &fec {
  318. pinctrl-names = "default";
  319. pinctrl-0 = <&pinctrl_fec>;
  320. phy-mode = "mii";
  321. phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
  322. phy-reset-duration = <1>;
  323. status = "okay";
  324. };
  325. &i2c1 {
  326. pinctrl-names = "default";
  327. pinctrl-0 = <&pinctrl_i2c1>;
  328. status = "okay";
  329. };
  330. &i2c2 {
  331. pinctrl-names = "default";
  332. pinctrl-0 = <&pinctrl_i2c2>;
  333. status = "okay";
  334. sgtl5000: codec@a {
  335. compatible = "fsl,sgtl5000";
  336. reg = <0x0a>;
  337. #sound-dai-cells = <0>;
  338. clocks = <&clk_audio>;
  339. VDDA-supply = <&vdig_reg>;
  340. VDDIO-supply = <&vvideo_reg>;
  341. };
  342. };
  343. &ipu_di0_disp1 {
  344. remote-endpoint = <&display0_in>;
  345. };
  346. &ipu_di1_disp2 {
  347. remote-endpoint = <&display1_in>;
  348. };
  349. &kpp {
  350. pinctrl-names = "default";
  351. pinctrl-0 = <&pinctrl_kpp>;
  352. linux,keymap = <
  353. MATRIX_KEY(0, 0, KEY_UP)
  354. MATRIX_KEY(0, 1, KEY_DOWN)
  355. MATRIX_KEY(0, 2, KEY_VOLUMEDOWN)
  356. MATRIX_KEY(0, 3, KEY_HOME)
  357. MATRIX_KEY(1, 0, KEY_RIGHT)
  358. MATRIX_KEY(1, 1, KEY_LEFT)
  359. MATRIX_KEY(1, 2, KEY_ENTER)
  360. MATRIX_KEY(1, 3, KEY_VOLUMEUP)
  361. MATRIX_KEY(2, 0, KEY_F6)
  362. MATRIX_KEY(2, 1, KEY_F8)
  363. MATRIX_KEY(2, 2, KEY_F9)
  364. MATRIX_KEY(2, 3, KEY_F10)
  365. MATRIX_KEY(3, 0, KEY_F1)
  366. MATRIX_KEY(3, 1, KEY_F2)
  367. MATRIX_KEY(3, 2, KEY_F3)
  368. MATRIX_KEY(3, 3, KEY_POWER)
  369. >;
  370. status = "okay";
  371. };
  372. &pmu {
  373. secure-reg-access;
  374. };
  375. &ssi2 {
  376. status = "okay";
  377. };
  378. &uart1 {
  379. pinctrl-names = "default";
  380. pinctrl-0 = <&pinctrl_uart1>;
  381. uart-has-rtscts;
  382. status = "okay";
  383. };
  384. &uart2 {
  385. pinctrl-names = "default";
  386. pinctrl-0 = <&pinctrl_uart2>;
  387. status = "okay";
  388. };
  389. &uart3 {
  390. pinctrl-names = "default";
  391. pinctrl-0 = <&pinctrl_uart3>;
  392. uart-has-rtscts;
  393. status = "okay";
  394. };
  395. &usbh1 {
  396. pinctrl-names = "default";
  397. pinctrl-0 = <&pinctrl_usbh1>;
  398. vbus-supply = <&reg_hub_reset>;
  399. fsl,usbphy = <&usbphy1>;
  400. phy_type = "ulpi";
  401. status = "okay";
  402. };
  403. &usbphy0 {
  404. vcc-supply = <&vusb_reg>;
  405. };
  406. &usbotg {
  407. dr_mode = "otg";
  408. disable-over-current;
  409. phy_type = "utmi_wide";
  410. status = "okay";
  411. };
  412. &iomuxc {
  413. imx51-babbage {
  414. pinctrl_audmux: audmuxgrp {
  415. fsl,pins = <
  416. MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
  417. MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
  418. MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
  419. MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
  420. >;
  421. };
  422. pinctrl_clk26mhz_audio: clk26mhzaudiocgrp {
  423. fsl,pins = <
  424. MX51_PAD_CSPI1_RDY__GPIO4_26 0x85
  425. >;
  426. };
  427. pinctrl_clk26mhz_osc: clk26mhzoscgrp {
  428. fsl,pins = <
  429. MX51_PAD_DI1_PIN12__GPIO3_1 0x85
  430. >;
  431. };
  432. pinctrl_clk26mhz_usb: clk26mhzusbgrp {
  433. fsl,pins = <
  434. MX51_PAD_EIM_D17__GPIO2_1 0x85
  435. >;
  436. };
  437. pinctrl_ecspi1: ecspi1grp {
  438. fsl,pins = <
  439. MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
  440. MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
  441. MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
  442. MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */
  443. MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 /* CS1 */
  444. >;
  445. };
  446. pinctrl_esdhc1: esdhc1grp {
  447. fsl,pins = <
  448. MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
  449. MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
  450. MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
  451. MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
  452. MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
  453. MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
  454. MX51_PAD_GPIO1_0__GPIO1_0 0x100
  455. MX51_PAD_GPIO1_1__GPIO1_1 0x100
  456. >;
  457. };
  458. pinctrl_esdhc2: esdhc2grp {
  459. fsl,pins = <
  460. MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
  461. MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
  462. MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
  463. MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
  464. MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
  465. MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
  466. MX51_PAD_GPIO1_5__GPIO1_5 0x100 /* WP */
  467. MX51_PAD_GPIO1_6__GPIO1_6 0x100 /* CD */
  468. >;
  469. };
  470. pinctrl_fec: fecgrp {
  471. fsl,pins = <
  472. MX51_PAD_EIM_EB2__FEC_MDIO 0x000001f5
  473. MX51_PAD_EIM_EB3__FEC_RDATA1 0x00000085
  474. MX51_PAD_EIM_CS2__FEC_RDATA2 0x00000085
  475. MX51_PAD_EIM_CS3__FEC_RDATA3 0x00000085
  476. MX51_PAD_EIM_CS4__FEC_RX_ER 0x00000180
  477. MX51_PAD_EIM_CS5__FEC_CRS 0x00000180
  478. MX51_PAD_NANDF_RB2__FEC_COL 0x00000180
  479. MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x00000180
  480. MX51_PAD_NANDF_D9__FEC_RDATA0 0x00002180
  481. MX51_PAD_NANDF_D8__FEC_TDATA0 0x00002004
  482. MX51_PAD_NANDF_CS2__FEC_TX_ER 0x00002004
  483. MX51_PAD_NANDF_CS3__FEC_MDC 0x00002004
  484. MX51_PAD_NANDF_CS4__FEC_TDATA1 0x00002004
  485. MX51_PAD_NANDF_CS5__FEC_TDATA2 0x00002004
  486. MX51_PAD_NANDF_CS6__FEC_TDATA3 0x00002004
  487. MX51_PAD_NANDF_CS7__FEC_TX_EN 0x00002004
  488. MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x00002180
  489. MX51_PAD_NANDF_D11__FEC_RX_DV 0x000020a4
  490. MX51_PAD_EIM_A20__GPIO2_14 0x00000085 /* Phy Reset */
  491. >;
  492. };
  493. pinctrl_gpio_keys: gpiokeysgrp {
  494. fsl,pins = <
  495. MX51_PAD_EIM_A27__GPIO2_21 0x5
  496. >;
  497. };
  498. pinctrl_gpio_leds: gpioledsgrp {
  499. fsl,pins = <
  500. MX51_PAD_EIM_D22__GPIO2_6 0x80000000
  501. >;
  502. };
  503. pinctrl_i2c1: i2c1grp {
  504. fsl,pins = <
  505. MX51_PAD_EIM_D19__I2C1_SCL 0x400001ed
  506. MX51_PAD_EIM_D16__I2C1_SDA 0x400001ed
  507. >;
  508. };
  509. pinctrl_i2c2: i2c2grp {
  510. fsl,pins = <
  511. MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
  512. MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
  513. >;
  514. };
  515. pinctrl_ipu_disp1: ipudisp1grp {
  516. fsl,pins = <
  517. MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
  518. MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
  519. MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
  520. MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
  521. MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
  522. MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
  523. MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
  524. MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
  525. MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
  526. MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
  527. MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
  528. MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
  529. MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
  530. MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
  531. MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
  532. MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
  533. MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
  534. MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
  535. MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
  536. MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
  537. MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
  538. MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
  539. MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
  540. MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
  541. MX51_PAD_DI1_PIN2__DI1_PIN2 0x5
  542. MX51_PAD_DI1_PIN3__DI1_PIN3 0x5
  543. >;
  544. };
  545. pinctrl_ipu_disp2: ipudisp2grp {
  546. fsl,pins = <
  547. MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5
  548. MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5
  549. MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5
  550. MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5
  551. MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5
  552. MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5
  553. MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5
  554. MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5
  555. MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5
  556. MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5
  557. MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5
  558. MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5
  559. MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5
  560. MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5
  561. MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5
  562. MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5
  563. MX51_PAD_DI2_PIN2__DI2_PIN2 0x5
  564. MX51_PAD_DI2_PIN3__DI2_PIN3 0x5
  565. MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
  566. MX51_PAD_DI_GP4__DI2_PIN15 0x5
  567. >;
  568. };
  569. pinctrl_kpp: kppgrp {
  570. fsl,pins = <
  571. MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
  572. MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
  573. MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
  574. MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
  575. MX51_PAD_KEY_COL0__KEY_COL0 0xe8
  576. MX51_PAD_KEY_COL1__KEY_COL1 0xe8
  577. MX51_PAD_KEY_COL2__KEY_COL2 0xe8
  578. MX51_PAD_KEY_COL3__KEY_COL3 0xe8
  579. >;
  580. };
  581. pinctrl_pmic: pmicgrp {
  582. fsl,pins = <
  583. MX51_PAD_GPIO1_8__GPIO1_8 0xe5 /* IRQ */
  584. >;
  585. };
  586. pinctrl_uart1: uart1grp {
  587. fsl,pins = <
  588. MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
  589. MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
  590. MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
  591. MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
  592. >;
  593. };
  594. pinctrl_uart2: uart2grp {
  595. fsl,pins = <
  596. MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
  597. MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
  598. >;
  599. };
  600. pinctrl_uart3: uart3grp {
  601. fsl,pins = <
  602. MX51_PAD_EIM_D25__UART3_RXD 0x1c5
  603. MX51_PAD_EIM_D26__UART3_TXD 0x1c5
  604. MX51_PAD_EIM_D27__UART3_RTS 0x1c5
  605. MX51_PAD_EIM_D24__UART3_CTS 0x1c5
  606. >;
  607. };
  608. pinctrl_usbh1: usbh1grp {
  609. fsl,pins = <
  610. MX51_PAD_USBH1_CLK__USBH1_CLK 0x80000000
  611. MX51_PAD_USBH1_DIR__USBH1_DIR 0x80000000
  612. MX51_PAD_USBH1_NXT__USBH1_NXT 0x80000000
  613. MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x80000000
  614. MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x80000000
  615. MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x80000000
  616. MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x80000000
  617. MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x80000000
  618. MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x80000000
  619. MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x80000000
  620. MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x80000000
  621. >;
  622. };
  623. pinctrl_usbh1reg: usbh1reggrp {
  624. fsl,pins = <
  625. MX51_PAD_EIM_D21__GPIO2_5 0x85
  626. >;
  627. };
  628. pinctrl_usbotgreg: usbotgreggrp {
  629. fsl,pins = <
  630. MX51_PAD_GPIO1_7__GPIO1_7 0x85
  631. >;
  632. };
  633. };
  634. };