imx50-evk.dts 2.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. //
  3. // Copyright 2013 Greg Ungerer <[email protected]>
  4. // Copyright 2011 Freescale Semiconductor, Inc.
  5. // Copyright 2011 Linaro Ltd.
  6. /dts-v1/;
  7. #include "imx50.dtsi"
  8. / {
  9. model = "Freescale i.MX50 Evaluation Kit";
  10. compatible = "fsl,imx50-evk", "fsl,imx50";
  11. memory@70000000 {
  12. device_type = "memory";
  13. reg = <0x70000000 0x80000000>;
  14. };
  15. };
  16. &cspi {
  17. pinctrl-names = "default";
  18. pinctrl-0 = <&pinctrl_cspi>;
  19. cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>, <&gpio4 13 GPIO_ACTIVE_LOW>;
  20. status = "okay";
  21. flash: m25p32@1 {
  22. #address-cells = <1>;
  23. #size-cells = <1>;
  24. compatible = "m25p32", "jedec,spi-nor";
  25. spi-max-frequency = <25000000>;
  26. reg = <1>;
  27. partition@0 {
  28. label = "bootloader";
  29. reg = <0x0 0x100000>;
  30. read-only;
  31. };
  32. partition@100000 {
  33. label = "kernel";
  34. reg = <0x100000 0x300000>;
  35. };
  36. };
  37. };
  38. &fec {
  39. pinctrl-names = "default";
  40. pinctrl-0 = <&pinctrl_fec>;
  41. phy-mode = "rmii";
  42. phy-reset-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
  43. status = "okay";
  44. };
  45. &iomuxc {
  46. imx50-evk {
  47. pinctrl_cspi: cspigrp {
  48. fsl,pins = <
  49. MX50_PAD_CSPI_SCLK__CSPI_SCLK 0x00
  50. MX50_PAD_CSPI_MISO__CSPI_MISO 0x00
  51. MX50_PAD_CSPI_MOSI__CSPI_MOSI 0x00
  52. MX50_PAD_CSPI_SS0__GPIO4_11 0xc4
  53. MX50_PAD_ECSPI1_MOSI__GPIO4_13 0x84
  54. >;
  55. };
  56. pinctrl_fec: fecgrp {
  57. fsl,pins = <
  58. MX50_PAD_SSI_RXFS__FEC_MDC 0x80
  59. MX50_PAD_SSI_RXC__FEC_MDIO 0x80
  60. MX50_PAD_DISP_D0__FEC_TX_CLK 0x80
  61. MX50_PAD_DISP_D1__FEC_RX_ERR 0x80
  62. MX50_PAD_DISP_D2__FEC_RX_DV 0x80
  63. MX50_PAD_DISP_D3__FEC_RDATA_1 0x80
  64. MX50_PAD_DISP_D4__FEC_RDATA_0 0x80
  65. MX50_PAD_DISP_D5__FEC_TX_EN 0x80
  66. MX50_PAD_DISP_D6__FEC_TDATA_1 0x80
  67. MX50_PAD_DISP_D7__FEC_TDATA_0 0x80
  68. >;
  69. };
  70. pinctrl_uart1: uart1grp {
  71. fsl,pins = <
  72. MX50_PAD_UART1_TXD__UART1_TXD_MUX 0x1e4
  73. MX50_PAD_UART1_RXD__UART1_RXD_MUX 0x1e4
  74. MX50_PAD_UART1_RTS__UART1_RTS 0x1e4
  75. MX50_PAD_UART1_CTS__UART1_CTS 0x1e4
  76. >;
  77. };
  78. };
  79. };
  80. &uart1 {
  81. pinctrl-names = "default";
  82. pinctrl-0 = <&pinctrl_uart1>;
  83. status = "okay";
  84. };
  85. &usbh1 {
  86. status = "okay";
  87. };
  88. &usbotg {
  89. status = "okay";
  90. };