imx27-phytec-phycard-s-rdk.dts 3.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright 2012 Markus Pargmann, Pengutronix
  4. */
  5. #include "imx27-phytec-phycard-s-som.dtsi"
  6. / {
  7. model = "Phytec pca100 rapid development kit";
  8. compatible = "phytec,imx27-pca100-rdk", "phytec,imx27-pca100", "fsl,imx27";
  9. chosen {
  10. stdout-path = &uart1;
  11. };
  12. display: display {
  13. model = "Primeview-PD050VL1";
  14. bits-per-pixel = <16>; /* non-standard but required */
  15. fsl,pcr = <0xf0c88080>; /* non-standard but required */
  16. display-timings {
  17. native-mode = <&timing0>;
  18. timing0: 640x480 {
  19. hactive = <640>;
  20. vactive = <480>;
  21. hback-porch = <112>;
  22. hfront-porch = <36>;
  23. hsync-len = <32>;
  24. vback-porch = <33>;
  25. vfront-porch = <33>;
  26. vsync-len = <2>;
  27. clock-frequency = <25000000>;
  28. };
  29. };
  30. };
  31. regulators {
  32. compatible = "simple-bus";
  33. #address-cells = <1>;
  34. #size-cells = <0>;
  35. reg_3v3: regulator@0 {
  36. compatible = "regulator-fixed";
  37. reg = <0>;
  38. regulator-name = "3V3";
  39. regulator-min-microvolt = <3300000>;
  40. regulator-max-microvolt = <3300000>;
  41. regulator-always-on;
  42. };
  43. };
  44. };
  45. &fb {
  46. display = <&display>;
  47. status = "okay";
  48. };
  49. &i2c1 {
  50. pinctrl-names = "default";
  51. pinctrl-0 = <&pinctrl_i2c1>;
  52. status = "okay";
  53. rtc@51 {
  54. compatible = "nxp,pcf8563";
  55. reg = <0x51>;
  56. };
  57. adc@64 {
  58. compatible = "maxim,max1037";
  59. vcc-supply = <&reg_3v3>;
  60. reg = <0x64>;
  61. };
  62. };
  63. &iomuxc {
  64. imx27-phycard-s-rdk {
  65. pinctrl_i2c1: i2c1grp {
  66. fsl,pins = <
  67. MX27_PAD_I2C_DATA__I2C_DATA 0x0
  68. MX27_PAD_I2C_CLK__I2C_CLK 0x0
  69. >;
  70. };
  71. pinctrl_owire1: owire1grp {
  72. fsl,pins = <
  73. MX27_PAD_RTCK__OWIRE 0x0
  74. >;
  75. };
  76. pinctrl_sdhc2: sdhc2grp {
  77. fsl,pins = <
  78. MX27_PAD_SD2_CLK__SD2_CLK 0x0
  79. MX27_PAD_SD2_CMD__SD2_CMD 0x0
  80. MX27_PAD_SD2_D0__SD2_D0 0x0
  81. MX27_PAD_SD2_D1__SD2_D1 0x0
  82. MX27_PAD_SD2_D2__SD2_D2 0x0
  83. MX27_PAD_SD2_D3__SD2_D3 0x0
  84. MX27_PAD_SSI3_RXDAT__GPIO3_29 0x0 /* CD */
  85. >;
  86. };
  87. pinctrl_uart1: uart1grp {
  88. fsl,pins = <
  89. MX27_PAD_UART1_TXD__UART1_TXD 0x0
  90. MX27_PAD_UART1_RXD__UART1_RXD 0x0
  91. MX27_PAD_UART1_CTS__UART1_CTS 0x0
  92. MX27_PAD_UART1_RTS__UART1_RTS 0x0
  93. >;
  94. };
  95. pinctrl_uart2: uart2grp {
  96. fsl,pins = <
  97. MX27_PAD_UART2_TXD__UART2_TXD 0x0
  98. MX27_PAD_UART2_RXD__UART2_RXD 0x0
  99. MX27_PAD_UART2_CTS__UART2_CTS 0x0
  100. MX27_PAD_UART2_RTS__UART2_RTS 0x0
  101. >;
  102. };
  103. pinctrl_uart3: uart3grp {
  104. fsl,pins = <
  105. MX27_PAD_UART3_TXD__UART3_TXD 0x0
  106. MX27_PAD_UART3_RXD__UART3_RXD 0x0
  107. MX27_PAD_UART3_CTS__UART3_CTS 0x0
  108. MX27_PAD_UART3_RTS__UART3_RTS 0x0
  109. >;
  110. };
  111. };
  112. };
  113. &owire {
  114. pinctrl-names = "default";
  115. pinctrl-0 = <&pinctrl_owire1>;
  116. status = "okay";
  117. };
  118. &sdhci2 {
  119. pinctrl-names = "default";
  120. pinctrl-0 = <&pinctrl_sdhc2>;
  121. cd-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
  122. status = "okay";
  123. };
  124. &uart1 {
  125. uart-has-rtscts;
  126. pinctrl-names = "default";
  127. pinctrl-0 = <&pinctrl_uart1>;
  128. status = "okay";
  129. };
  130. &uart2 {
  131. uart-has-rtscts;
  132. pinctrl-names = "default";
  133. pinctrl-0 = <&pinctrl_uart2>;
  134. status = "okay";
  135. };
  136. &uart3 {
  137. uart-has-rtscts;
  138. pinctrl-names = "default";
  139. pinctrl-0 = <&pinctrl_uart3>;
  140. status = "okay";
  141. };