imx27-eukrea-cpuimx27.dtsi 6.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 2014 Alexander Shiyan <[email protected]>
  4. */
  5. /dts-v1/;
  6. #include "imx27.dtsi"
  7. / {
  8. model = "Eukrea CPUIMX27";
  9. compatible = "eukrea,cpuimx27", "fsl,imx27";
  10. memory@a0000000 {
  11. device_type = "memory";
  12. reg = <0xa0000000 0x04000000>;
  13. };
  14. clk14745600: clk-uart {
  15. compatible = "fixed-clock";
  16. #clock-cells = <0>;
  17. clock-frequency = <14745600>;
  18. };
  19. };
  20. &fec {
  21. pinctrl-names = "default";
  22. pinctrl-0 = <&pinctrl_fec>;
  23. status = "okay";
  24. };
  25. &i2c1 {
  26. pinctrl-names = "default";
  27. pinctrl-0 = <&pinctrl_i2c1>;
  28. status = "okay";
  29. pcf8563@51 {
  30. compatible = "nxp,pcf8563";
  31. reg = <0x51>;
  32. };
  33. };
  34. &nfc {
  35. pinctrl-names = "default";
  36. pinctrl-0 = <&pinctrl_nfc>;
  37. nand-bus-width = <8>;
  38. nand-ecc-mode = "hw";
  39. nand-on-flash-bbt;
  40. status = "okay";
  41. };
  42. &owire {
  43. pinctrl-names = "default";
  44. pinctrl-0 = <&pinctrl_owire>;
  45. status = "okay";
  46. };
  47. &sdhci2 {
  48. pinctrl-names = "default";
  49. pinctrl-0 = <&pinctrl_sdhc2>;
  50. bus-width = <4>;
  51. non-removable;
  52. status = "okay";
  53. };
  54. &uart4 {
  55. pinctrl-names = "default";
  56. pinctrl-0 = <&pinctrl_uart4>;
  57. uart-has-rtscts;
  58. status = "okay";
  59. };
  60. &usbh2 {
  61. pinctrl-names = "default";
  62. pinctrl-0 = <&pinctrl_usbh2>;
  63. dr_mode = "host";
  64. phy_type = "ulpi";
  65. disable-over-current;
  66. status = "okay";
  67. };
  68. &usbotg {
  69. pinctrl-names = "default";
  70. pinctrl-0 = <&pinctrl_usbotg>;
  71. dr_mode = "otg";
  72. phy_type = "ulpi";
  73. disable-over-current;
  74. status = "okay";
  75. };
  76. &weim {
  77. status = "okay";
  78. nor: nor@0,0 {
  79. #address-cells = <1>;
  80. #size-cells = <1>;
  81. compatible = "cfi-flash";
  82. reg = <0 0x00000000 0x04000000>;
  83. bank-width = <2>;
  84. linux,mtd-name = "physmap-flash.0";
  85. fsl,weim-cs-timing = <0x00008f03 0xa0330d01 0x002208c0>;
  86. };
  87. uart8250@3,200000 {
  88. pinctrl-names = "default";
  89. pinctrl-0 = <&pinctrl_uart8250_1>;
  90. compatible = "ns8250";
  91. clocks = <&clk14745600>;
  92. fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
  93. interrupts = <&gpio2 23 IRQ_TYPE_LEVEL_LOW>;
  94. reg = <3 0x200000 0x1000>;
  95. reg-shift = <1>;
  96. reg-io-width = <1>;
  97. no-loopback-test;
  98. };
  99. uart8250@3,400000 {
  100. pinctrl-names = "default";
  101. pinctrl-0 = <&pinctrl_uart8250_2>;
  102. compatible = "ns8250";
  103. clocks = <&clk14745600>;
  104. fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
  105. interrupts = <&gpio2 22 IRQ_TYPE_LEVEL_LOW>;
  106. reg = <3 0x400000 0x1000>;
  107. reg-shift = <1>;
  108. reg-io-width = <1>;
  109. no-loopback-test;
  110. };
  111. uart8250@3,800000 {
  112. pinctrl-names = "default";
  113. pinctrl-0 = <&pinctrl_uart8250_3>;
  114. compatible = "ns8250";
  115. clocks = <&clk14745600>;
  116. fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
  117. interrupts = <&gpio2 27 IRQ_TYPE_LEVEL_LOW>;
  118. reg = <3 0x800000 0x1000>;
  119. reg-shift = <1>;
  120. reg-io-width = <1>;
  121. no-loopback-test;
  122. };
  123. uart8250@3,1000000 {
  124. pinctrl-names = "default";
  125. pinctrl-0 = <&pinctrl_uart8250_4>;
  126. compatible = "ns8250";
  127. clocks = <&clk14745600>;
  128. fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
  129. interrupts = <&gpio2 30 IRQ_TYPE_LEVEL_LOW>;
  130. reg = <3 0x1000000 0x1000>;
  131. reg-shift = <1>;
  132. reg-io-width = <1>;
  133. no-loopback-test;
  134. };
  135. };
  136. &iomuxc {
  137. imx27-eukrea-cpuimx27 {
  138. pinctrl_fec: fecgrp {
  139. fsl,pins = <
  140. MX27_PAD_SD3_CMD__FEC_TXD0 0x0
  141. MX27_PAD_SD3_CLK__FEC_TXD1 0x0
  142. MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
  143. MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
  144. MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
  145. MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
  146. MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
  147. MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
  148. MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
  149. MX27_PAD_ATA_DATA7__FEC_MDC 0x0
  150. MX27_PAD_ATA_DATA8__FEC_CRS 0x0
  151. MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
  152. MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
  153. MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
  154. MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
  155. MX27_PAD_ATA_DATA13__FEC_COL 0x0
  156. MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
  157. MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
  158. >;
  159. };
  160. pinctrl_i2c1: i2c1grp {
  161. fsl,pins = <
  162. MX27_PAD_I2C_DATA__I2C_DATA 0x0
  163. MX27_PAD_I2C_CLK__I2C_CLK 0x0
  164. >;
  165. };
  166. pinctrl_nfc: nfcgrp {
  167. fsl,pins = <
  168. MX27_PAD_NFRB__NFRB 0x0
  169. MX27_PAD_NFCLE__NFCLE 0x0
  170. MX27_PAD_NFWP_B__NFWP_B 0x0
  171. MX27_PAD_NFCE_B__NFCE_B 0x0
  172. MX27_PAD_NFALE__NFALE 0x0
  173. MX27_PAD_NFRE_B__NFRE_B 0x0
  174. MX27_PAD_NFWE_B__NFWE_B 0x0
  175. >;
  176. };
  177. pinctrl_owire: owiregrp {
  178. fsl,pins = <
  179. MX27_PAD_RTCK__OWIRE 0x0
  180. >;
  181. };
  182. pinctrl_sdhc2: sdhc2grp {
  183. fsl,pins = <
  184. MX27_PAD_SD2_CLK__SD2_CLK 0x0
  185. MX27_PAD_SD2_CMD__SD2_CMD 0x0
  186. MX27_PAD_SD2_D0__SD2_D0 0x0
  187. MX27_PAD_SD2_D1__SD2_D1 0x0
  188. MX27_PAD_SD2_D2__SD2_D2 0x0
  189. MX27_PAD_SD2_D3__SD2_D3 0x0
  190. >;
  191. };
  192. pinctrl_uart4: uart4grp {
  193. fsl,pins = <
  194. MX27_PAD_USBH1_TXDM__UART4_TXD 0x0
  195. MX27_PAD_USBH1_RXDP__UART4_RXD 0x0
  196. MX27_PAD_USBH1_TXDP__UART4_CTS 0x0
  197. MX27_PAD_USBH1_FS__UART4_RTS 0x0
  198. >;
  199. };
  200. pinctrl_uart8250_1: uart82501grp {
  201. fsl,pins = <
  202. MX27_PAD_USB_PWR__GPIO2_23 0x0
  203. >;
  204. };
  205. pinctrl_uart8250_2: uart82502grp {
  206. fsl,pins = <
  207. MX27_PAD_USBH1_SUSP__GPIO2_22 0x0
  208. >;
  209. };
  210. pinctrl_uart8250_3: uart82503grp {
  211. fsl,pins = <
  212. MX27_PAD_USBH1_OE_B__GPIO2_27 0x0
  213. >;
  214. };
  215. pinctrl_uart8250_4: uart82504grp {
  216. fsl,pins = <
  217. MX27_PAD_USBH1_RXDM__GPIO2_30 0x0
  218. >;
  219. };
  220. pinctrl_usbh2: usbh2grp {
  221. fsl,pins = <
  222. MX27_PAD_USBH2_CLK__USBH2_CLK 0x0
  223. MX27_PAD_USBH2_DIR__USBH2_DIR 0x0
  224. MX27_PAD_USBH2_NXT__USBH2_NXT 0x0
  225. MX27_PAD_USBH2_STP__USBH2_STP 0x0
  226. MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0
  227. MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0
  228. MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0
  229. MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0
  230. MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0
  231. MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0
  232. MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0
  233. MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0
  234. >;
  235. };
  236. pinctrl_usbotg: usbotggrp {
  237. fsl,pins = <
  238. MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0
  239. MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0
  240. MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0
  241. MX27_PAD_USBOTG_STP__USBOTG_STP 0x0
  242. MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0
  243. MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0
  244. MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0
  245. MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0
  246. MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0
  247. MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0
  248. MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0
  249. MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0
  250. >;
  251. };
  252. };
  253. };