imx25-pdk.dts 6.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. //
  3. // Copyright 2013 Freescale Semiconductor, Inc.
  4. /dts-v1/;
  5. #include <dt-bindings/gpio/gpio.h>
  6. #include <dt-bindings/input/input.h>
  7. #include "imx25.dtsi"
  8. / {
  9. model = "Freescale i.MX25 Product Development Kit";
  10. compatible = "fsl,imx25-pdk", "fsl,imx25";
  11. memory@80000000 {
  12. device_type = "memory";
  13. reg = <0x80000000 0x4000000>;
  14. };
  15. regulators {
  16. compatible = "simple-bus";
  17. #address-cells = <1>;
  18. #size-cells = <0>;
  19. reg_fec_3v3: regulator@0 {
  20. compatible = "regulator-fixed";
  21. reg = <0>;
  22. regulator-name = "fec-3v3";
  23. regulator-min-microvolt = <3300000>;
  24. regulator-max-microvolt = <3300000>;
  25. gpio = <&gpio2 3 0>;
  26. enable-active-high;
  27. };
  28. reg_2p5v: regulator@1 {
  29. compatible = "regulator-fixed";
  30. reg = <1>;
  31. regulator-name = "2P5V";
  32. regulator-min-microvolt = <2500000>;
  33. regulator-max-microvolt = <2500000>;
  34. };
  35. reg_3p3v: regulator@2 {
  36. compatible = "regulator-fixed";
  37. reg = <2>;
  38. regulator-name = "3P3V";
  39. regulator-min-microvolt = <3300000>;
  40. regulator-max-microvolt = <3300000>;
  41. };
  42. reg_can_3v3: regulator@3 {
  43. compatible = "regulator-fixed";
  44. reg = <3>;
  45. regulator-name = "can-3v3";
  46. regulator-min-microvolt = <3300000>;
  47. regulator-max-microvolt = <3300000>;
  48. gpio = <&gpio4 6 0>;
  49. };
  50. };
  51. sound {
  52. compatible = "fsl,imx25-pdk-sgtl5000",
  53. "fsl,imx-audio-sgtl5000";
  54. model = "imx25-pdk-sgtl5000";
  55. ssi-controller = <&ssi1>;
  56. audio-codec = <&codec>;
  57. audio-routing =
  58. "MIC_IN", "Mic Jack",
  59. "Mic Jack", "Mic Bias",
  60. "Headphone Jack", "HP_OUT";
  61. mux-int-port = <1>;
  62. mux-ext-port = <4>;
  63. };
  64. wvga: display {
  65. model = "CLAA057VC01CW";
  66. bits-per-pixel = <16>;
  67. fsl,pcr = <0xfa208b80>;
  68. bus-width = <18>;
  69. display-timings {
  70. native-mode = <&wvga_timings>;
  71. wvga_timings: 640x480 {
  72. hactive = <640>;
  73. vactive = <480>;
  74. hback-porch = <45>;
  75. hfront-porch = <114>;
  76. hsync-len = <1>;
  77. vback-porch = <33>;
  78. vfront-porch = <11>;
  79. vsync-len = <1>;
  80. clock-frequency = <25200000>;
  81. };
  82. };
  83. };
  84. };
  85. &audmux {
  86. pinctrl-names = "default";
  87. pinctrl-0 = <&pinctrl_audmux>;
  88. status = "okay";
  89. };
  90. &can1 {
  91. pinctrl-names = "default";
  92. pinctrl-0 = <&pinctrl_can1>;
  93. xceiver-supply = <&reg_can_3v3>;
  94. status = "okay";
  95. };
  96. &esdhc1 {
  97. pinctrl-names = "default";
  98. pinctrl-0 = <&pinctrl_esdhc1>;
  99. cd-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
  100. wp-gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>;
  101. status = "okay";
  102. };
  103. &fec {
  104. phy-mode = "rmii";
  105. pinctrl-names = "default";
  106. pinctrl-0 = <&pinctrl_fec>;
  107. phy-supply = <&reg_fec_3v3>;
  108. phy-reset-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;
  109. status = "okay";
  110. };
  111. &i2c1 {
  112. clock-frequency = <100000>;
  113. pinctrl-names = "default";
  114. pinctrl-0 = <&pinctrl_i2c1>;
  115. status = "okay";
  116. codec: sgtl5000@a {
  117. compatible = "fsl,sgtl5000";
  118. reg = <0x0a>;
  119. clocks = <&clks 129>;
  120. VDDA-supply = <&reg_2p5v>;
  121. VDDIO-supply = <&reg_3p3v>;
  122. };
  123. };
  124. &iomuxc {
  125. imx25-pdk {
  126. pinctrl_audmux: audmuxgrp {
  127. fsl,pins = <
  128. MX25_PAD_RW__AUD4_TXFS 0xe0
  129. MX25_PAD_OE__AUD4_TXC 0xe0
  130. MX25_PAD_EB0__AUD4_TXD 0xe0
  131. MX25_PAD_EB1__AUD4_RXD 0xe0
  132. >;
  133. };
  134. pinctrl_can1: can1grp {
  135. fsl,pins = <
  136. MX25_PAD_GPIO_A__CAN1_TX 0x0
  137. MX25_PAD_GPIO_B__CAN1_RX 0x0
  138. MX25_PAD_D14__GPIO_4_6 0x80000000
  139. >;
  140. };
  141. pinctrl_esdhc1: esdhc1grp {
  142. fsl,pins = <
  143. MX25_PAD_SD1_CMD__ESDHC1_CMD 0x80000000
  144. MX25_PAD_SD1_CLK__ESDHC1_CLK 0x80000000
  145. MX25_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000
  146. MX25_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000
  147. MX25_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000
  148. MX25_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000
  149. MX25_PAD_A14__GPIO_2_0 0x80000000
  150. MX25_PAD_A15__GPIO_2_1 0x80000000
  151. >;
  152. };
  153. pinctrl_fec: fecgrp {
  154. fsl,pins = <
  155. MX25_PAD_FEC_MDC__FEC_MDC 0x80000000
  156. MX25_PAD_FEC_MDIO__FEC_MDIO 0x400001e0
  157. MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000
  158. MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000
  159. MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
  160. MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000
  161. MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000
  162. MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000
  163. MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1c0
  164. MX25_PAD_A17__GPIO_2_3 0x80000000
  165. MX25_PAD_D12__GPIO_4_8 0x80000000
  166. >;
  167. };
  168. pinctrl_i2c1: i2c1grp {
  169. fsl,pins = <
  170. MX25_PAD_I2C1_CLK__I2C1_CLK 0x80000000
  171. MX25_PAD_I2C1_DAT__I2C1_DAT 0x80000000
  172. >;
  173. };
  174. pinctrl_kpp: kppgrp {
  175. fsl,pins = <
  176. MX25_PAD_KPP_ROW0__KPP_ROW0 0x80000000
  177. MX25_PAD_KPP_ROW1__KPP_ROW1 0x80000000
  178. MX25_PAD_KPP_ROW2__KPP_ROW2 0x80000000
  179. MX25_PAD_KPP_ROW3__KPP_ROW3 0x80000000
  180. MX25_PAD_KPP_COL0__KPP_COL0 0x80000000
  181. MX25_PAD_KPP_COL1__KPP_COL1 0x80000000
  182. MX25_PAD_KPP_COL2__KPP_COL2 0x80000000
  183. MX25_PAD_KPP_COL3__KPP_COL3 0x80000000
  184. >;
  185. };
  186. pinctrl_lcd: lcdgrp {
  187. fsl,pins = <
  188. MX25_PAD_LD0__LD0 0xe0
  189. MX25_PAD_LD1__LD1 0xe0
  190. MX25_PAD_LD2__LD2 0xe0
  191. MX25_PAD_LD3__LD3 0xe0
  192. MX25_PAD_LD4__LD4 0xe0
  193. MX25_PAD_LD5__LD5 0xe0
  194. MX25_PAD_LD6__LD6 0xe0
  195. MX25_PAD_LD7__LD7 0xe0
  196. MX25_PAD_LD8__LD8 0xe0
  197. MX25_PAD_LD9__LD9 0xe0
  198. MX25_PAD_LD10__LD10 0xe0
  199. MX25_PAD_LD11__LD11 0xe0
  200. MX25_PAD_LD12__LD12 0xe0
  201. MX25_PAD_LD13__LD13 0xe0
  202. MX25_PAD_LD14__LD14 0xe0
  203. MX25_PAD_LD15__LD15 0xe0
  204. MX25_PAD_GPIO_E__LD16 0xe0
  205. MX25_PAD_GPIO_F__LD17 0xe0
  206. MX25_PAD_HSYNC__HSYNC 0xe0
  207. MX25_PAD_VSYNC__VSYNC 0xe0
  208. MX25_PAD_LSCLK__LSCLK 0xe0
  209. MX25_PAD_OE_ACD__OE_ACD 0xe0
  210. MX25_PAD_CONTRAST__CONTRAST 0xe0
  211. >;
  212. };
  213. pinctrl_uart1: uart1grp {
  214. fsl,pins = <
  215. MX25_PAD_UART1_RTS__UART1_RTS 0xe0
  216. MX25_PAD_UART1_CTS__UART1_CTS 0xe0
  217. MX25_PAD_UART1_TXD__UART1_TXD 0x80000000
  218. MX25_PAD_UART1_RXD__UART1_RXD 0xc0
  219. >;
  220. };
  221. };
  222. };
  223. &lcdc {
  224. display = <&wvga>;
  225. fsl,lpccr = <0x00a903ff>;
  226. fsl,lscr1 = <0x00120300>;
  227. fsl,dmacr = <0x00020010>;
  228. pinctrl-names = "default";
  229. pinctrl-0 = <&pinctrl_lcd>;
  230. status = "okay";
  231. };
  232. &nfc {
  233. nand-on-flash-bbt;
  234. status = "okay";
  235. };
  236. &kpp {
  237. pinctrl-names = "default";
  238. pinctrl-0 = <&pinctrl_kpp>;
  239. linux,keymap = <
  240. MATRIX_KEY(0x0, 0x0, KEY_UP)
  241. MATRIX_KEY(0x0, 0x1, KEY_DOWN)
  242. MATRIX_KEY(0x0, 0x2, KEY_VOLUMEDOWN)
  243. MATRIX_KEY(0x0, 0x3, KEY_HOME)
  244. MATRIX_KEY(0x1, 0x0, KEY_RIGHT)
  245. MATRIX_KEY(0x1, 0x1, KEY_LEFT)
  246. MATRIX_KEY(0x1, 0x2, KEY_ENTER)
  247. MATRIX_KEY(0x1, 0x3, KEY_VOLUMEUP)
  248. MATRIX_KEY(0x2, 0x0, KEY_F6)
  249. MATRIX_KEY(0x2, 0x1, KEY_F8)
  250. MATRIX_KEY(0x2, 0x2, KEY_F9)
  251. MATRIX_KEY(0x2, 0x3, KEY_F10)
  252. MATRIX_KEY(0x3, 0x0, KEY_F1)
  253. MATRIX_KEY(0x3, 0x1, KEY_F2)
  254. MATRIX_KEY(0x3, 0x2, KEY_F3)
  255. MATRIX_KEY(0x3, 0x2, KEY_POWER)
  256. >;
  257. status = "okay";
  258. };
  259. &ssi1 {
  260. status = "okay";
  261. };
  262. &tsc {
  263. status = "okay";
  264. };
  265. &tscadc {
  266. status = "okay";
  267. };
  268. &uart1 {
  269. pinctrl-names = "default";
  270. pinctrl-0 = <&pinctrl_uart1>;
  271. uart-has-rtscts;
  272. status = "okay";
  273. };
  274. &usbhost1 {
  275. status = "okay";
  276. };
  277. &usbotg {
  278. external-vbus-divider;
  279. status = "okay";
  280. };