imx1-ads.dts 2.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 2014 Alexander Shiyan <[email protected]>
  4. */
  5. /dts-v1/;
  6. #include "imx1.dtsi"
  7. / {
  8. model = "Freescale MX1 ADS";
  9. compatible = "fsl,imx1ads", "fsl,imx1";
  10. chosen {
  11. stdout-path = &uart1;
  12. };
  13. memory@8000000 {
  14. device_type = "memory";
  15. reg = <0x08000000 0x04000000>;
  16. };
  17. };
  18. &cspi1 {
  19. pinctrl-0 = <&pinctrl_cspi1>;
  20. cs-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
  21. status = "okay";
  22. };
  23. &i2c {
  24. pinctrl-names = "default";
  25. pinctrl-0 = <&pinctrl_i2c>;
  26. status = "okay";
  27. extgpio0: pcf8575@22 {
  28. compatible = "nxp,pcf8575";
  29. reg = <0x22>;
  30. gpio-controller;
  31. #gpio-cells = <2>;
  32. };
  33. extgpio1: pcf8575@24 {
  34. compatible = "nxp,pcf8575";
  35. reg = <0x24>;
  36. gpio-controller;
  37. #gpio-cells = <2>;
  38. };
  39. };
  40. &uart1 {
  41. pinctrl-names = "default";
  42. pinctrl-0 = <&pinctrl_uart1>;
  43. uart-has-rtscts;
  44. status = "okay";
  45. };
  46. &uart2 {
  47. pinctrl-names = "default";
  48. pinctrl-0 = <&pinctrl_uart2>;
  49. uart-has-rtscts;
  50. status = "okay";
  51. };
  52. &weim {
  53. pinctrl-names = "default";
  54. pinctrl-0 = <&pinctrl_weim>;
  55. status = "okay";
  56. nor: nor@0,0 {
  57. compatible = "cfi-flash";
  58. reg = <0 0x00000000 0x02000000>;
  59. bank-width = <4>;
  60. fsl,weim-cs-timing = <0x00003e00 0x00000801>;
  61. #address-cells = <1>;
  62. #size-cells = <1>;
  63. };
  64. };
  65. &iomuxc {
  66. imx1-ads {
  67. pinctrl_cspi1: cspi1grp {
  68. fsl,pins = <
  69. MX1_PAD_SPI1_MISO__SPI1_MISO 0x0
  70. MX1_PAD_SPI1_MOSI__SPI1_MOSI 0x0
  71. MX1_PAD_SPI1_RDY__SPI1_RDY 0x0
  72. MX1_PAD_SPI1_SCLK__SPI1_SCLK 0x0
  73. MX1_PAD_SPI1_SS__GPIO3_15 0x0
  74. >;
  75. };
  76. pinctrl_i2c: i2cgrp {
  77. fsl,pins = <
  78. MX1_PAD_I2C_SCL__I2C_SCL 0x0
  79. MX1_PAD_I2C_SDA__I2C_SDA 0x0
  80. >;
  81. };
  82. pinctrl_uart1: uart1grp {
  83. fsl,pins = <
  84. MX1_PAD_UART1_TXD__UART1_TXD 0x0
  85. MX1_PAD_UART1_RXD__UART1_RXD 0x0
  86. MX1_PAD_UART1_CTS__UART1_CTS 0x0
  87. MX1_PAD_UART1_RTS__UART1_RTS 0x0
  88. >;
  89. };
  90. pinctrl_uart2: uart2grp {
  91. fsl,pins = <
  92. MX1_PAD_UART2_TXD__UART2_TXD 0x0
  93. MX1_PAD_UART2_RXD__UART2_RXD 0x0
  94. MX1_PAD_UART2_CTS__UART2_CTS 0x0
  95. MX1_PAD_UART2_RTS__UART2_RTS 0x0
  96. >;
  97. };
  98. pinctrl_weim: weimgrp {
  99. fsl,pins = <
  100. MX1_PAD_A0__A0 0x0
  101. MX1_PAD_A16__A16 0x0
  102. MX1_PAD_A17__A17 0x0
  103. MX1_PAD_A18__A18 0x0
  104. MX1_PAD_A19__A19 0x0
  105. MX1_PAD_A20__A20 0x0
  106. MX1_PAD_A21__A21 0x0
  107. MX1_PAD_A22__A22 0x0
  108. MX1_PAD_A23__A23 0x0
  109. MX1_PAD_A24__A24 0x0
  110. MX1_PAD_BCLK__BCLK 0x0
  111. MX1_PAD_CS4__CS4 0x0
  112. MX1_PAD_DTACK__DTACK 0x0
  113. MX1_PAD_ECB__ECB 0x0
  114. MX1_PAD_LBA__LBA 0x0
  115. >;
  116. };
  117. };
  118. };