gemini-dlink-dir-685.dts 11 KB

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  1. /*
  2. * Device Tree file for D-Link DIR-685 Xtreme N Storage Router
  3. */
  4. /dts-v1/;
  5. #include "gemini.dtsi"
  6. #include <dt-bindings/input/input.h>
  7. / {
  8. model = "D-Link DIR-685 Xtreme N Storage Router";
  9. compatible = "dlink,dir-685", "cortina,gemini";
  10. #address-cells = <1>;
  11. #size-cells = <1>;
  12. memory@0 {
  13. /* 128 MB SDRAM in 2 x Hynix HY5DU121622DTP-D43 */
  14. device_type = "memory";
  15. reg = <0x00000000 0x8000000>;
  16. };
  17. chosen {
  18. bootargs = "console=ttyS0,19200n8 root=/dev/sda1 rw rootwait consoleblank=300";
  19. stdout-path = "uart0:19200n8";
  20. };
  21. gpio_keys {
  22. compatible = "gpio-keys";
  23. button-esc {
  24. debounce-interval = <100>;
  25. wakeup-source;
  26. linux,code = <KEY_ESC>;
  27. label = "reset";
  28. /* Collides with LPC_LAD[0], UART DCD, SSP 97RST */
  29. gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
  30. };
  31. button-eject {
  32. debounce-interval = <100>;
  33. wakeup-source;
  34. linux,code = <KEY_EJECTCD>;
  35. label = "unmount";
  36. /* Collides with LPC LFRAME, UART RTS, SSP TXD */
  37. gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
  38. };
  39. };
  40. vdisp: regulator {
  41. compatible = "regulator-fixed";
  42. regulator-name = "display-power";
  43. regulator-min-microvolt = <3600000>;
  44. regulator-max-microvolt = <3600000>;
  45. /* Collides with LCD E */
  46. gpio = <&gpio0 16 GPIO_ACTIVE_HIGH>;
  47. enable-active-high;
  48. };
  49. spi {
  50. compatible = "spi-gpio";
  51. #address-cells = <1>;
  52. #size-cells = <0>;
  53. /* Collides with IDE pins, that's cool (we do not use them) */
  54. sck-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
  55. miso-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
  56. mosi-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
  57. cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
  58. num-chipselects = <1>;
  59. panel: display@0 {
  60. compatible = "dlink,dir-685-panel", "ilitek,ili9322";
  61. reg = <0>;
  62. /* 50 ns min period = 20 MHz */
  63. spi-max-frequency = <20000000>;
  64. vcc-supply = <&vdisp>;
  65. iovcc-supply = <&vdisp>;
  66. vci-supply = <&vdisp>;
  67. port {
  68. panel_in: endpoint {
  69. remote-endpoint = <&display_out>;
  70. };
  71. };
  72. };
  73. };
  74. leds {
  75. compatible = "gpio-leds";
  76. led-wps {
  77. label = "dir685:blue:WPS";
  78. /* Collides with ICE */
  79. gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
  80. default-state = "on";
  81. linux,default-trigger = "heartbeat";
  82. };
  83. /*
  84. * These two LEDs are on the side of the device.
  85. * For electrical reasons, both LEDs cannot be active
  86. * at the same time so only blue or orange can be on at
  87. * one time. Enabling both makes the LED go dark.
  88. * The LEDs both sit inside the unmount button and the
  89. * label on the case says "unmount".
  90. */
  91. led-blue-hd {
  92. label = "dir685:blue:HD";
  93. /* Collides with LPC_SERIRQ, UART DTR, SSP FSC pins */
  94. gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
  95. default-state = "off";
  96. linux,default-trigger = "disk-read";
  97. };
  98. led-orange-hd {
  99. label = "dir685:orange:HD";
  100. /* Collides with LPC_LAD[2], UART DSR, SSP ECLK pins */
  101. gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
  102. default-state = "off";
  103. linux,default-trigger = "disk-write";
  104. };
  105. };
  106. /*
  107. * This is a Sunon Maglev GM0502PFV2-8 cooling fan @10000 RPM.
  108. * sensor. It is turned on when the temperature exceeds 46 degrees
  109. * and turned off when the temperatures goes below 41 degrees
  110. * (celsius).
  111. */
  112. fan0: gpio-fan {
  113. compatible = "gpio-fan";
  114. /* Collides with IDE */
  115. gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
  116. gpio-fan,speed-map = <0 0>, <10000 1>;
  117. #cooling-cells = <2>;
  118. };
  119. thermal-zones {
  120. chassis-thermal {
  121. /* Poll every 20 seconds */
  122. polling-delay = <20000>;
  123. /* Poll every 2nd second when cooling */
  124. polling-delay-passive = <2000>;
  125. /* Use the thermal sensor in the hard drive */
  126. thermal-sensors = <&drive0>;
  127. /* Tripping points from the fan.script in the rootfs */
  128. trips {
  129. alert: chassis-alert {
  130. /* At 43 degrees turn on the fan */
  131. temperature = <43000>;
  132. hysteresis = <3000>;
  133. type = "active";
  134. };
  135. crit: chassis-crit {
  136. /* Just shut down at 60 degrees */
  137. temperature = <60000>;
  138. hysteresis = <2000>;
  139. type = "critical";
  140. };
  141. };
  142. cooling-maps {
  143. map0 {
  144. trip = <&alert>;
  145. cooling-device = <&fan0 1 1>;
  146. };
  147. };
  148. };
  149. };
  150. /*
  151. * The touchpad input is connected to a GPIO bit-banged
  152. * I2C bus.
  153. */
  154. i2c {
  155. compatible = "i2c-gpio";
  156. /* Collides with ICE */
  157. sda-gpios = <&gpio0 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
  158. scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
  159. #address-cells = <1>;
  160. #size-cells = <0>;
  161. touchkeys@26 {
  162. compatible = "dlink,dir685-touchkeys";
  163. reg = <0x26>;
  164. interrupt-parent = <&gpio0>;
  165. /* Collides with NAND flash */
  166. interrupts = <17 IRQ_TYPE_EDGE_FALLING>;
  167. };
  168. };
  169. /* This is a RealTek RTL8366RB switch and PHY using SMI over GPIO */
  170. switch {
  171. compatible = "realtek,rtl8366rb";
  172. /* 22 = MDIO (has input reads), 21 = MDC (clock, output only) */
  173. mdc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;
  174. mdio-gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;
  175. reset-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
  176. realtek,disable-leds;
  177. switch_intc: interrupt-controller {
  178. /* GPIO 15 provides the interrupt */
  179. interrupt-parent = <&gpio0>;
  180. interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
  181. interrupt-controller;
  182. #address-cells = <0>;
  183. #interrupt-cells = <1>;
  184. };
  185. ports {
  186. #address-cells = <1>;
  187. #size-cells = <0>;
  188. port@0 {
  189. reg = <0>;
  190. label = "lan0";
  191. phy-handle = <&phy0>;
  192. };
  193. port@1 {
  194. reg = <1>;
  195. label = "lan1";
  196. phy-handle = <&phy1>;
  197. };
  198. port@2 {
  199. reg = <2>;
  200. label = "lan2";
  201. phy-handle = <&phy2>;
  202. };
  203. port@3 {
  204. reg = <3>;
  205. label = "lan3";
  206. phy-handle = <&phy3>;
  207. };
  208. port@4 {
  209. reg = <4>;
  210. label = "wan";
  211. phy-handle = <&phy4>;
  212. };
  213. rtl8366rb_cpu_port: port@5 {
  214. reg = <5>;
  215. label = "cpu";
  216. ethernet = <&gmac0>;
  217. phy-mode = "rgmii";
  218. fixed-link {
  219. speed = <1000>;
  220. full-duplex;
  221. pause;
  222. };
  223. };
  224. };
  225. mdio {
  226. compatible = "realtek,smi-mdio";
  227. #address-cells = <1>;
  228. #size-cells = <0>;
  229. phy0: phy@0 {
  230. reg = <0>;
  231. interrupt-parent = <&switch_intc>;
  232. interrupts = <0>;
  233. };
  234. phy1: phy@1 {
  235. reg = <1>;
  236. interrupt-parent = <&switch_intc>;
  237. interrupts = <1>;
  238. };
  239. phy2: phy@2 {
  240. reg = <2>;
  241. interrupt-parent = <&switch_intc>;
  242. interrupts = <2>;
  243. };
  244. phy3: phy@3 {
  245. reg = <3>;
  246. interrupt-parent = <&switch_intc>;
  247. interrupts = <3>;
  248. };
  249. phy4: phy@4 {
  250. reg = <4>;
  251. interrupt-parent = <&switch_intc>;
  252. interrupts = <12>;
  253. };
  254. };
  255. };
  256. soc {
  257. flash@30000000 {
  258. /*
  259. * Flash access collides with the Chip Enable signal for
  260. * the display panel, that reuse the parallel flash Chip
  261. * Select 1 (CS1). We switch the pin control state so we
  262. * enable these pins for flash access only when we need
  263. * then, and when disabled they can be used for GPIO which
  264. * is what the display panel needs.
  265. */
  266. status = "okay";
  267. pinctrl-names = "enabled", "disabled";
  268. pinctrl-0 = <&pflash_default_pins>;
  269. pinctrl-1 = <&pflash_disabled_pins>;
  270. /* 32MB of flash */
  271. reg = <0x30000000 0x02000000>;
  272. partitions {
  273. compatible = "fixed-partitions";
  274. #address-cells = <1>;
  275. #size-cells = <1>;
  276. /*
  277. * This "RedBoot" is the Storlink derivative.
  278. */
  279. partition@0 {
  280. label = "RedBoot";
  281. reg = <0x00000000 0x00040000>;
  282. read-only;
  283. };
  284. /*
  285. * This firmware image contains the kernel catenated
  286. * with the squashfs root filesystem. For some reason
  287. * this is called "upgrade" on the vendor system.
  288. */
  289. partition@40000 {
  290. label = "upgrade";
  291. reg = <0x00040000 0x01f40000>;
  292. read-only;
  293. };
  294. /* RGDB, Residental Gateway Database? */
  295. partition@1f80000 {
  296. label = "rgdb";
  297. reg = <0x01f80000 0x00040000>;
  298. read-only;
  299. };
  300. /*
  301. * This partition contains MAC addresses for WAN,
  302. * WLAN and LAN, and the country code (for wireless
  303. * I guess).
  304. */
  305. partition@1fc0000 {
  306. label = "nvram";
  307. reg = <0x01fc0000 0x00020000>;
  308. read-only;
  309. };
  310. partition@1fe0000 {
  311. label = "LangPack";
  312. reg = <0x01fe0000 0x00020000>;
  313. read-only;
  314. };
  315. };
  316. };
  317. syscon: syscon@40000000 {
  318. pinctrl {
  319. /*
  320. * gpio0bgrp cover line 5, 6 used by TK I2C
  321. * gpio0bgrp cover line 7 used by WPS LED
  322. * gpio0cgrp cover line 8, 13 used by keys
  323. * and 11, 12 used by the HD LEDs
  324. * and line 14, 15 used by RTL8366
  325. * RESET and phy ready
  326. * gpio0egrp cover line 16 used by VDISP
  327. * gpio0fgrp cover line 17 used by TK IRQ
  328. * gpio0ggrp cover line 20 used by panel CS
  329. * gpio0hgrp cover line 21,22 used by RTL8366RB MDIO
  330. */
  331. gpio0_default_pins: pinctrl-gpio0 {
  332. mux {
  333. function = "gpio0";
  334. groups = "gpio0bgrp",
  335. "gpio0cgrp",
  336. "gpio0egrp",
  337. "gpio0fgrp",
  338. "gpio0hgrp";
  339. };
  340. };
  341. /*
  342. * gpio1bgrp cover line 5,8,7 used by panel SPI
  343. * also line 6 used by the fan
  344. *
  345. */
  346. gpio1_default_pins: pinctrl-gpio1 {
  347. mux {
  348. function = "gpio1";
  349. groups = "gpio1bgrp";
  350. };
  351. };
  352. /*
  353. * These GPIO groups will be mapped in over some
  354. * of the flash pins when the flash is not in
  355. * active use.
  356. */
  357. pflash_disabled_pins: pinctrl-pflash-disabled {
  358. mux {
  359. function = "gpio0";
  360. groups = "gpio0ggrp", "gpio0igrp", "gpio0jgrp",
  361. "gpio0kgrp";
  362. };
  363. };
  364. pinctrl-gmii {
  365. mux {
  366. function = "gmii";
  367. groups = "gmii_gmac0_grp";
  368. };
  369. conf0 {
  370. pins = "V8 GMAC0 RXDV", "T10 GMAC1 RXDV",
  371. "Y7 GMAC0 RXC", "Y11 GMAC1 RXC",
  372. "T8 GMAC0 TXEN", "W11 GMAC1 TXEN",
  373. "U8 GMAC0 TXC", "V11 GMAC1 TXC",
  374. "W8 GMAC0 RXD0", "V9 GMAC0 RXD1",
  375. "Y8 GMAC0 RXD2", "U9 GMAC0 RXD3",
  376. "T7 GMAC0 TXD0", "U6 GMAC0 TXD1",
  377. "V7 GMAC0 TXD2", "U7 GMAC0 TXD3",
  378. "Y12 GMAC1 RXD0", "V12 GMAC1 RXD1",
  379. "T11 GMAC1 RXD2", "W12 GMAC1 RXD3",
  380. "U10 GMAC1 TXD0", "Y10 GMAC1 TXD1",
  381. "W10 GMAC1 TXD2", "T9 GMAC1 TXD3";
  382. skew-delay = <7>;
  383. };
  384. /* Set up drive strength on GMAC0 to 16 mA */
  385. conf1 {
  386. groups = "gmii_gmac0_grp";
  387. drive-strength = <16>;
  388. };
  389. };
  390. };
  391. };
  392. sata: sata@46000000 {
  393. cortina,gemini-ata-muxmode = <0>;
  394. cortina,gemini-enable-sata-bridge;
  395. status = "okay";
  396. };
  397. gpio0: gpio@4d000000 {
  398. pinctrl-names = "default";
  399. pinctrl-0 = <&gpio0_default_pins>;
  400. };
  401. gpio1: gpio@4e000000 {
  402. pinctrl-names = "default";
  403. pinctrl-0 = <&gpio1_default_pins>;
  404. };
  405. pci@50000000 {
  406. status = "okay";
  407. };
  408. ethernet@60000000 {
  409. status = "okay";
  410. ethernet-port@0 {
  411. phy-mode = "rgmii";
  412. fixed-link {
  413. speed = <1000>;
  414. full-duplex;
  415. pause;
  416. };
  417. };
  418. ethernet-port@1 {
  419. /* Not used in this platform */
  420. };
  421. };
  422. ide@63000000 {
  423. status = "okay";
  424. /*
  425. * This drive may have a temperature sensor with a
  426. * thermal zone we can use for thermal control of the
  427. * chassis temperature using the fan.
  428. */
  429. drive0: ide-port@0 {
  430. reg = <0>;
  431. #thermal-sensor-cells = <0>;
  432. };
  433. };
  434. display-controller@6a000000 {
  435. status = "okay";
  436. port {
  437. display_out: endpoint {
  438. remote-endpoint = <&panel_in>;
  439. };
  440. };
  441. };
  442. usb@68000000 {
  443. status = "okay";
  444. };
  445. usb@69000000 {
  446. status = "okay";
  447. };
  448. };
  449. };