exynos5.dtsi 6.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Samsung's Exynos5 SoC series common device tree source
  4. *
  5. * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
  6. * http://www.samsung.com
  7. *
  8. * Samsung's Exynos5 SoC series device nodes are listed in this file. Particular
  9. * SoCs from Exynos5 series can include this file and provide values for SoCs
  10. * specfic bindings.
  11. */
  12. #include <dt-bindings/interrupt-controller/arm-gic.h>
  13. #include <dt-bindings/interrupt-controller/irq.h>
  14. / {
  15. interrupt-parent = <&gic>;
  16. #address-cells = <1>;
  17. #size-cells = <1>;
  18. aliases {
  19. i2c0 = &i2c_0;
  20. i2c1 = &i2c_1;
  21. i2c2 = &i2c_2;
  22. i2c3 = &i2c_3;
  23. serial0 = &serial_0;
  24. serial1 = &serial_1;
  25. serial2 = &serial_2;
  26. serial3 = &serial_3;
  27. };
  28. soc: soc {
  29. compatible = "simple-bus";
  30. #address-cells = <1>;
  31. #size-cells = <1>;
  32. ranges;
  33. chipid: chipid@10000000 {
  34. compatible = "samsung,exynos4210-chipid";
  35. reg = <0x10000000 0x100>;
  36. };
  37. sromc: memory-controller@12250000 {
  38. compatible = "samsung,exynos4210-srom";
  39. reg = <0x12250000 0x14>;
  40. };
  41. combiner: interrupt-controller@10440000 {
  42. compatible = "samsung,exynos4210-combiner";
  43. #interrupt-cells = <2>;
  44. interrupt-controller;
  45. samsung,combiner-nr = <32>;
  46. reg = <0x10440000 0x1000>;
  47. interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  48. <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
  49. <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
  50. <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
  51. <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
  52. <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
  53. <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
  54. <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
  55. <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
  56. <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
  57. <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
  58. <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
  59. <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
  60. <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
  61. <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
  62. <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
  63. <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
  64. <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
  65. <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
  66. <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
  67. <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
  68. <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
  69. <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
  70. <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
  71. <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
  72. <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
  73. <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
  74. <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
  75. <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
  76. <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
  77. <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
  78. <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
  79. };
  80. gic: interrupt-controller@10481000 {
  81. compatible = "arm,gic-400", "arm,cortex-a15-gic";
  82. #interrupt-cells = <3>;
  83. interrupt-controller;
  84. reg = <0x10481000 0x1000>,
  85. <0x10482000 0x2000>,
  86. <0x10484000 0x2000>,
  87. <0x10486000 0x2000>;
  88. interrupts = <GIC_PPI 9
  89. (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  90. };
  91. sysreg_system_controller: syscon@10050000 {
  92. compatible = "samsung,exynos5-sysreg", "syscon";
  93. reg = <0x10050000 0x5000>;
  94. };
  95. serial_0: serial@12c00000 {
  96. compatible = "samsung,exynos4210-uart";
  97. reg = <0x12C00000 0x100>;
  98. interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
  99. };
  100. serial_1: serial@12c10000 {
  101. compatible = "samsung,exynos4210-uart";
  102. reg = <0x12C10000 0x100>;
  103. interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
  104. };
  105. serial_2: serial@12c20000 {
  106. compatible = "samsung,exynos4210-uart";
  107. reg = <0x12C20000 0x100>;
  108. interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
  109. };
  110. serial_3: serial@12c30000 {
  111. compatible = "samsung,exynos4210-uart";
  112. reg = <0x12C30000 0x100>;
  113. interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
  114. };
  115. i2c_0: i2c@12c60000 {
  116. compatible = "samsung,s3c2440-i2c";
  117. reg = <0x12C60000 0x100>;
  118. interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
  119. #address-cells = <1>;
  120. #size-cells = <0>;
  121. samsung,sysreg-phandle = <&sysreg_system_controller>;
  122. status = "disabled";
  123. };
  124. i2c_1: i2c@12c70000 {
  125. compatible = "samsung,s3c2440-i2c";
  126. reg = <0x12C70000 0x100>;
  127. interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
  128. #address-cells = <1>;
  129. #size-cells = <0>;
  130. samsung,sysreg-phandle = <&sysreg_system_controller>;
  131. status = "disabled";
  132. };
  133. i2c_2: i2c@12c80000 {
  134. compatible = "samsung,s3c2440-i2c";
  135. reg = <0x12C80000 0x100>;
  136. interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
  137. #address-cells = <1>;
  138. #size-cells = <0>;
  139. samsung,sysreg-phandle = <&sysreg_system_controller>;
  140. status = "disabled";
  141. };
  142. i2c_3: i2c@12c90000 {
  143. compatible = "samsung,s3c2440-i2c";
  144. reg = <0x12C90000 0x100>;
  145. interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
  146. #address-cells = <1>;
  147. #size-cells = <0>;
  148. samsung,sysreg-phandle = <&sysreg_system_controller>;
  149. status = "disabled";
  150. };
  151. pwm: pwm@12dd0000 {
  152. compatible = "samsung,exynos4210-pwm";
  153. reg = <0x12DD0000 0x100>;
  154. interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
  155. <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
  156. <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
  157. <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
  158. <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
  159. samsung,pwm-outputs = <0>, <1>, <2>, <3>;
  160. #pwm-cells = <3>;
  161. };
  162. rtc: rtc@101e0000 {
  163. compatible = "samsung,s3c6410-rtc";
  164. reg = <0x101E0000 0x100>;
  165. interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
  166. <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
  167. status = "disabled";
  168. };
  169. fimd: fimd@14400000 {
  170. compatible = "samsung,exynos5250-fimd";
  171. interrupt-parent = <&combiner>;
  172. reg = <0x14400000 0x40000>;
  173. interrupt-names = "fifo", "vsync", "lcd_sys";
  174. interrupts = <18 4>, <18 5>, <18 6>;
  175. samsung,sysreg = <&sysreg_system_controller>;
  176. status = "disabled";
  177. };
  178. dp: dp-controller@145b0000 {
  179. compatible = "samsung,exynos5-dp";
  180. reg = <0x145B0000 0x1000>;
  181. interrupts = <10 3>;
  182. interrupt-parent = <&combiner>;
  183. status = "disabled";
  184. };
  185. sss: sss@10830000 {
  186. compatible = "samsung,exynos4210-secss";
  187. reg = <0x10830000 0x300>;
  188. interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
  189. };
  190. prng: rng@10830400 {
  191. compatible = "samsung,exynos5250-prng";
  192. reg = <0x10830400 0x200>;
  193. };
  194. trng: rng@10830600 {
  195. compatible = "samsung,exynos5250-trng";
  196. reg = <0x10830600 0x100>;
  197. };
  198. g2d: g2d@10850000 {
  199. compatible = "samsung,exynos5250-g2d";
  200. reg = <0x10850000 0x1000>;
  201. interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
  202. status = "disabled";
  203. };
  204. };
  205. };