ecx-common.dtsi 4.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright 2011-2012 Calxeda, Inc.
  4. */
  5. / {
  6. chosen {
  7. bootargs = "console=ttyAMA0";
  8. };
  9. psci {
  10. compatible = "arm,psci";
  11. method = "smc";
  12. cpu_suspend = <0x84000002>;
  13. cpu_off = <0x84000004>;
  14. cpu_on = <0x84000006>;
  15. };
  16. soc {
  17. #address-cells = <1>;
  18. #size-cells = <1>;
  19. compatible = "simple-bus";
  20. interrupt-parent = <&intc>;
  21. sata@ffe08000 {
  22. compatible = "calxeda,hb-ahci";
  23. reg = <0xffe08000 0x10000>;
  24. interrupts = <0 83 4>;
  25. dma-coherent;
  26. calxeda,port-phys = < &combophy5 0>, <&combophy0 0>,
  27. <&combophy0 1>, <&combophy0 2>,
  28. <&combophy0 3>;
  29. calxeda,sgpio-gpio =<&gpioh 5 1>, <&gpioh 6 1>,
  30. <&gpioh 7 1>;
  31. calxeda,led-order = <4 0 1 2 3>;
  32. };
  33. sdhci@ffe0e000 {
  34. compatible = "calxeda,hb-sdhci";
  35. reg = <0xffe0e000 0x1000>;
  36. interrupts = <0 90 4>;
  37. clocks = <&eclk>;
  38. status = "disabled";
  39. };
  40. ipc@fff20000 {
  41. compatible = "arm,pl320", "arm,primecell";
  42. reg = <0xfff20000 0x1000>;
  43. interrupts = <0 7 4>;
  44. clocks = <&pclk>;
  45. clock-names = "apb_pclk";
  46. };
  47. gpioe: gpio@fff30000 {
  48. #gpio-cells = <2>;
  49. compatible = "arm,pl061", "arm,primecell";
  50. gpio-controller;
  51. reg = <0xfff30000 0x1000>;
  52. interrupts = <0 14 4>;
  53. clocks = <&pclk>;
  54. clock-names = "apb_pclk";
  55. status = "disabled";
  56. };
  57. gpiof: gpio@fff31000 {
  58. #gpio-cells = <2>;
  59. compatible = "arm,pl061", "arm,primecell";
  60. gpio-controller;
  61. reg = <0xfff31000 0x1000>;
  62. interrupts = <0 15 4>;
  63. clocks = <&pclk>;
  64. clock-names = "apb_pclk";
  65. status = "disabled";
  66. };
  67. gpiog: gpio@fff32000 {
  68. #gpio-cells = <2>;
  69. compatible = "arm,pl061", "arm,primecell";
  70. gpio-controller;
  71. reg = <0xfff32000 0x1000>;
  72. interrupts = <0 16 4>;
  73. clocks = <&pclk>;
  74. clock-names = "apb_pclk";
  75. status = "disabled";
  76. };
  77. gpioh: gpio@fff33000 {
  78. #gpio-cells = <2>;
  79. compatible = "arm,pl061", "arm,primecell";
  80. gpio-controller;
  81. reg = <0xfff33000 0x1000>;
  82. interrupts = <0 17 4>;
  83. clocks = <&pclk>;
  84. clock-names = "apb_pclk";
  85. status = "disabled";
  86. };
  87. timer@fff34000 {
  88. compatible = "arm,sp804", "arm,primecell";
  89. reg = <0xfff34000 0x1000>;
  90. interrupts = <0 18 4>;
  91. clocks = <&pclk>;
  92. clock-names = "apb_pclk";
  93. };
  94. rtc@fff35000 {
  95. compatible = "arm,pl031", "arm,primecell";
  96. reg = <0xfff35000 0x1000>;
  97. interrupts = <0 19 4>;
  98. clocks = <&pclk>;
  99. clock-names = "apb_pclk";
  100. };
  101. serial@fff36000 {
  102. compatible = "arm,pl011", "arm,primecell";
  103. reg = <0xfff36000 0x1000>;
  104. interrupts = <0 20 4>;
  105. clocks = <&pclk>, <&pclk>;
  106. clock-names = "uartclk", "apb_pclk";
  107. };
  108. smic@fff3a000 {
  109. compatible = "ipmi-smic";
  110. device_type = "ipmi";
  111. reg = <0xfff3a000 0x1000>;
  112. interrupts = <0 24 4>;
  113. reg-size = <4>;
  114. reg-spacing = <4>;
  115. };
  116. sregs@fff3c000 {
  117. compatible = "calxeda,hb-sregs";
  118. reg = <0xfff3c000 0x1000>;
  119. clocks {
  120. #address-cells = <1>;
  121. #size-cells = <0>;
  122. osc: oscillator {
  123. #clock-cells = <0>;
  124. compatible = "fixed-clock";
  125. clock-frequency = <33333000>;
  126. };
  127. ddrpll: ddrpll {
  128. #clock-cells = <0>;
  129. compatible = "calxeda,hb-pll-clock";
  130. clocks = <&osc>;
  131. reg = <0x108>;
  132. };
  133. a9pll: a9pll {
  134. #clock-cells = <0>;
  135. compatible = "calxeda,hb-pll-clock";
  136. clocks = <&osc>;
  137. reg = <0x100>;
  138. };
  139. a9periphclk: a9periphclk {
  140. #clock-cells = <0>;
  141. compatible = "calxeda,hb-a9periph-clock";
  142. clocks = <&a9pll>;
  143. reg = <0x104>;
  144. };
  145. a9bclk: a9bclk {
  146. #clock-cells = <0>;
  147. compatible = "calxeda,hb-a9bus-clock";
  148. clocks = <&a9pll>;
  149. reg = <0x104>;
  150. };
  151. emmcpll: emmcpll {
  152. #clock-cells = <0>;
  153. compatible = "calxeda,hb-pll-clock";
  154. clocks = <&osc>;
  155. reg = <0x10C>;
  156. };
  157. eclk: eclk {
  158. #clock-cells = <0>;
  159. compatible = "calxeda,hb-emmc-clock";
  160. clocks = <&emmcpll>;
  161. reg = <0x114>;
  162. };
  163. pclk: pclk {
  164. #clock-cells = <0>;
  165. compatible = "fixed-clock";
  166. clock-frequency = <150000000>;
  167. };
  168. };
  169. };
  170. dma@fff3d000 {
  171. compatible = "arm,pl330", "arm,primecell";
  172. reg = <0xfff3d000 0x1000>;
  173. interrupts = <0 92 4>;
  174. clocks = <&pclk>;
  175. clock-names = "apb_pclk";
  176. };
  177. ethernet@fff50000 {
  178. compatible = "calxeda,hb-xgmac";
  179. reg = <0xfff50000 0x1000>;
  180. interrupts = <0 77 4>, <0 78 4>, <0 79 4>;
  181. dma-coherent;
  182. };
  183. ethernet@fff51000 {
  184. compatible = "calxeda,hb-xgmac";
  185. reg = <0xfff51000 0x1000>;
  186. interrupts = <0 80 4>, <0 81 4>, <0 82 4>;
  187. dma-coherent;
  188. };
  189. combophy0: combo-phy@fff58000 {
  190. compatible = "calxeda,hb-combophy";
  191. #phy-cells = <1>;
  192. reg = <0xfff58000 0x1000>;
  193. phydev = <5>;
  194. };
  195. combophy5: combo-phy@fff5d000 {
  196. compatible = "calxeda,hb-combophy";
  197. #phy-cells = <1>;
  198. reg = <0xfff5d000 0x1000>;
  199. phydev = <31>;
  200. };
  201. };
  202. };