dra72-evm.dts 2.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/
  4. */
  5. #include "dra72-evm-common.dtsi"
  6. #include "dra72x-mmc-iodelay.dtsi"
  7. / {
  8. model = "TI DRA722";
  9. memory@0 {
  10. device_type = "memory";
  11. reg = <0x0 0x80000000 0x0 0x40000000>; /* 1024 MB */
  12. };
  13. reserved-memory {
  14. #address-cells = <2>;
  15. #size-cells = <2>;
  16. ranges;
  17. ipu2_memory_region: ipu2-memory@95800000 {
  18. compatible = "shared-dma-pool";
  19. reg = <0x0 0x95800000 0x0 0x3800000>;
  20. reusable;
  21. status = "okay";
  22. };
  23. dsp1_memory_region: dsp1-memory@99000000 {
  24. compatible = "shared-dma-pool";
  25. reg = <0x0 0x99000000 0x0 0x4000000>;
  26. reusable;
  27. status = "okay";
  28. };
  29. ipu1_memory_region: ipu1-memory@9d000000 {
  30. compatible = "shared-dma-pool";
  31. reg = <0x0 0x9d000000 0x0 0x2000000>;
  32. reusable;
  33. status = "okay";
  34. };
  35. };
  36. evm_1v8_sw: fixedregulator-evm_1v8 {
  37. compatible = "regulator-fixed";
  38. regulator-name = "evm_1v8";
  39. regulator-min-microvolt = <1800000>;
  40. regulator-max-microvolt = <1800000>;
  41. vin-supply = <&smps4_reg>;
  42. regulator-always-on;
  43. regulator-boot-on;
  44. };
  45. };
  46. &i2c1 {
  47. tps65917: tps65917@58 {
  48. reg = <0x58>;
  49. interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
  50. };
  51. };
  52. #include "dra72-evm-tps65917.dtsi"
  53. &hdmi {
  54. vdda-supply = <&ldo3_reg>;
  55. };
  56. &pcf_gpio_21 {
  57. interrupt-parent = <&gpio6>;
  58. interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
  59. };
  60. &mac_sw {
  61. mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_HIGH>;
  62. status = "okay";
  63. };
  64. &cpsw_port1 {
  65. phy-handle = <&ethphy0>;
  66. phy-mode = "rgmii";
  67. ti,dual-emac-pvid = <1>;
  68. };
  69. &cpsw_port2 {
  70. status = "disabled";
  71. };
  72. &davinci_mdio_sw {
  73. ethphy0: ethernet-phy@3 {
  74. reg = <3>;
  75. };
  76. };
  77. &mmc1 {
  78. pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
  79. pinctrl-0 = <&mmc1_pins_default>;
  80. pinctrl-1 = <&mmc1_pins_hs>;
  81. pinctrl-2 = <&mmc1_pins_sdr12>;
  82. pinctrl-3 = <&mmc1_pins_sdr25>;
  83. pinctrl-4 = <&mmc1_pins_sdr50>;
  84. pinctrl-5 = <&mmc1_pins_ddr50_rev10>;
  85. pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev10_conf>;
  86. vqmmc-supply = <&ldo1_reg>;
  87. };
  88. &mmc2 {
  89. pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
  90. pinctrl-0 = <&mmc2_pins_default>;
  91. pinctrl-1 = <&mmc2_pins_hs>;
  92. pinctrl-2 = <&mmc2_pins_ddr_rev10>;
  93. pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev10_conf>;
  94. vmmc-supply = <&evm_1v8_sw>;
  95. };
  96. &ipu2 {
  97. status = "okay";
  98. memory-region = <&ipu2_memory_region>;
  99. };
  100. &ipu1 {
  101. status = "okay";
  102. memory-region = <&ipu1_memory_region>;
  103. };
  104. &dsp1 {
  105. status = "okay";
  106. memory-region = <&dsp1_memory_region>;
  107. };