dra7.dtsi 36 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
  4. *
  5. * Based on "omap4.dtsi"
  6. */
  7. #include <dt-bindings/bus/ti-sysc.h>
  8. #include <dt-bindings/clock/dra7.h>
  9. #include <dt-bindings/interrupt-controller/arm-gic.h>
  10. #include <dt-bindings/pinctrl/dra.h>
  11. #include <dt-bindings/clock/dra7.h>
  12. #define MAX_SOURCES 400
  13. / {
  14. #address-cells = <2>;
  15. #size-cells = <2>;
  16. compatible = "ti,dra7xx";
  17. interrupt-parent = <&crossbar_mpu>;
  18. chosen { };
  19. aliases {
  20. i2c0 = &i2c1;
  21. i2c1 = &i2c2;
  22. i2c2 = &i2c3;
  23. i2c3 = &i2c4;
  24. i2c4 = &i2c5;
  25. serial0 = &uart1;
  26. serial1 = &uart2;
  27. serial2 = &uart3;
  28. serial3 = &uart4;
  29. serial4 = &uart5;
  30. serial5 = &uart6;
  31. serial6 = &uart7;
  32. serial7 = &uart8;
  33. serial8 = &uart9;
  34. serial9 = &uart10;
  35. ethernet0 = &cpsw_port1;
  36. ethernet1 = &cpsw_port2;
  37. d_can0 = &dcan1;
  38. d_can1 = &dcan2;
  39. spi0 = &qspi;
  40. };
  41. timer {
  42. compatible = "arm,armv7-timer";
  43. status = "disabled"; /* See ARM architected timer wrap erratum i940 */
  44. interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  45. <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  46. <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  47. <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
  48. interrupt-parent = <&gic>;
  49. };
  50. gic: interrupt-controller@48211000 {
  51. compatible = "arm,cortex-a15-gic";
  52. interrupt-controller;
  53. #interrupt-cells = <3>;
  54. reg = <0x0 0x48211000 0x0 0x1000>,
  55. <0x0 0x48212000 0x0 0x2000>,
  56. <0x0 0x48214000 0x0 0x2000>,
  57. <0x0 0x48216000 0x0 0x2000>;
  58. interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  59. interrupt-parent = <&gic>;
  60. };
  61. wakeupgen: interrupt-controller@48281000 {
  62. compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
  63. interrupt-controller;
  64. #interrupt-cells = <3>;
  65. reg = <0x0 0x48281000 0x0 0x1000>;
  66. interrupt-parent = <&gic>;
  67. };
  68. cpus {
  69. #address-cells = <1>;
  70. #size-cells = <0>;
  71. cpu0: cpu@0 {
  72. device_type = "cpu";
  73. compatible = "arm,cortex-a15";
  74. reg = <0>;
  75. operating-points-v2 = <&cpu0_opp_table>;
  76. clocks = <&dpll_mpu_ck>;
  77. clock-names = "cpu";
  78. clock-latency = <300000>; /* From omap-cpufreq driver */
  79. /* cooling options */
  80. #cooling-cells = <2>; /* min followed by max */
  81. vbb-supply = <&abb_mpu>;
  82. };
  83. };
  84. cpu0_opp_table: opp-table {
  85. compatible = "operating-points-v2-ti-cpu";
  86. syscon = <&scm_wkup>;
  87. opp_nom-1000000000 {
  88. opp-hz = /bits/ 64 <1000000000>;
  89. opp-microvolt = <1060000 850000 1150000>,
  90. <1060000 850000 1150000>;
  91. opp-supported-hw = <0xFF 0x01>;
  92. opp-suspend;
  93. };
  94. opp_od-1176000000 {
  95. opp-hz = /bits/ 64 <1176000000>;
  96. opp-microvolt = <1160000 885000 1160000>,
  97. <1160000 885000 1160000>;
  98. opp-supported-hw = <0xFF 0x02>;
  99. };
  100. opp_high@1500000000 {
  101. opp-hz = /bits/ 64 <1500000000>;
  102. opp-microvolt = <1210000 950000 1250000>,
  103. <1210000 950000 1250000>;
  104. opp-supported-hw = <0xFF 0x04>;
  105. };
  106. };
  107. /*
  108. * XXX: Use a flat representation of the SOC interconnect.
  109. * The real OMAP interconnect network is quite complex.
  110. * Since it will not bring real advantage to represent that in DT for
  111. * the moment, just use a fake OCP bus entry to represent the whole bus
  112. * hierarchy.
  113. */
  114. ocp: ocp {
  115. compatible = "simple-pm-bus";
  116. power-domains = <&prm_core>;
  117. clocks = <&l3main1_clkctrl DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL 0>,
  118. <&l3instr_clkctrl DRA7_L3INSTR_L3_MAIN_2_CLKCTRL 0>;
  119. #address-cells = <1>;
  120. #size-cells = <1>;
  121. ranges = <0x0 0x0 0x0 0xc0000000>;
  122. dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
  123. l3-noc@44000000 {
  124. compatible = "ti,dra7-l3-noc";
  125. reg = <0x44000000 0x1000>,
  126. <0x45000000 0x1000>;
  127. interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
  128. <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
  129. };
  130. l4_cfg: interconnect@4a000000 {
  131. };
  132. l4_wkup: interconnect@4ae00000 {
  133. };
  134. l4_per1: interconnect@48000000 {
  135. };
  136. target-module@48210000 {
  137. compatible = "ti,sysc-omap4-simple", "ti,sysc";
  138. power-domains = <&prm_mpu>;
  139. clocks = <&mpu_clkctrl DRA7_MPU_MPU_CLKCTRL 0>;
  140. clock-names = "fck";
  141. #address-cells = <1>;
  142. #size-cells = <1>;
  143. ranges = <0 0x48210000 0x1f0000>;
  144. mpu {
  145. compatible = "ti,omap5-mpu";
  146. };
  147. };
  148. l4_per2: interconnect@48400000 {
  149. };
  150. l4_per3: interconnect@48800000 {
  151. };
  152. /*
  153. * Register access seems to have complex dependencies and also
  154. * seems to need an enabled phy. See the TRM chapter for "Table
  155. * 26-678. Main Sequence PCIe Controller Global Initialization"
  156. * and also dra7xx_pcie_probe().
  157. */
  158. axi0: target-module@51000000 {
  159. compatible = "ti,sysc-omap4", "ti,sysc";
  160. power-domains = <&prm_l3init>;
  161. resets = <&prm_l3init 0>;
  162. reset-names = "rstctrl";
  163. clocks = <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 0>,
  164. <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 9>,
  165. <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 10>;
  166. clock-names = "fck", "phy-clk", "phy-clk-div";
  167. #size-cells = <1>;
  168. #address-cells = <1>;
  169. ranges = <0x51000000 0x51000000 0x3000>,
  170. <0x20000000 0x20000000 0x10000000>;
  171. dma-ranges;
  172. /**
  173. * To enable PCI endpoint mode, disable the pcie1_rc
  174. * node and enable pcie1_ep mode.
  175. */
  176. pcie1_rc: pcie@51000000 {
  177. reg = <0x51000000 0x2000>,
  178. <0x51002000 0x14c>,
  179. <0x20001000 0x2000>;
  180. reg-names = "rc_dbics", "ti_conf", "config";
  181. interrupts = <0 232 0x4>, <0 233 0x4>;
  182. #address-cells = <3>;
  183. #size-cells = <2>;
  184. device_type = "pci";
  185. ranges = <0x81000000 0 0x00000000 0x20003000 0 0x00010000>,
  186. <0x82000000 0 0x20013000 0x20013000 0 0x0ffed000>;
  187. bus-range = <0x00 0xff>;
  188. #interrupt-cells = <1>;
  189. num-lanes = <1>;
  190. linux,pci-domain = <0>;
  191. phys = <&pcie1_phy>;
  192. phy-names = "pcie-phy0";
  193. ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
  194. interrupt-map-mask = <0 0 0 7>;
  195. interrupt-map = <0 0 0 1 &pcie1_intc 1>,
  196. <0 0 0 2 &pcie1_intc 2>,
  197. <0 0 0 3 &pcie1_intc 3>,
  198. <0 0 0 4 &pcie1_intc 4>;
  199. ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
  200. status = "disabled";
  201. pcie1_intc: interrupt-controller {
  202. interrupt-controller;
  203. #address-cells = <0>;
  204. #interrupt-cells = <1>;
  205. };
  206. };
  207. pcie1_ep: pcie_ep@51000000 {
  208. reg = <0x51000000 0x28>,
  209. <0x51002000 0x14c>,
  210. <0x51001000 0x28>,
  211. <0x20001000 0x10000000>;
  212. reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
  213. interrupts = <0 232 0x4>;
  214. num-lanes = <1>;
  215. num-ib-windows = <4>;
  216. num-ob-windows = <16>;
  217. phys = <&pcie1_phy>;
  218. phy-names = "pcie-phy0";
  219. ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
  220. ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
  221. status = "disabled";
  222. };
  223. };
  224. /*
  225. * Register access seems to have complex dependencies and also
  226. * seems to need an enabled phy. See the TRM chapter for "Table
  227. * 26-678. Main Sequence PCIe Controller Global Initialization"
  228. * and also dra7xx_pcie_probe().
  229. */
  230. axi1: target-module@51800000 {
  231. compatible = "ti,sysc-omap4", "ti,sysc";
  232. clocks = <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 0>,
  233. <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 9>,
  234. <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 10>;
  235. clock-names = "fck", "phy-clk", "phy-clk-div";
  236. power-domains = <&prm_l3init>;
  237. resets = <&prm_l3init 1>;
  238. reset-names = "rstctrl";
  239. #size-cells = <1>;
  240. #address-cells = <1>;
  241. ranges = <0x51800000 0x51800000 0x3000>,
  242. <0x30000000 0x30000000 0x10000000>;
  243. dma-ranges;
  244. status = "disabled";
  245. pcie2_rc: pcie@51800000 {
  246. reg = <0x51800000 0x2000>,
  247. <0x51802000 0x14c>,
  248. <0x30001000 0x2000>;
  249. reg-names = "rc_dbics", "ti_conf", "config";
  250. interrupts = <0 355 0x4>, <0 356 0x4>;
  251. #address-cells = <3>;
  252. #size-cells = <2>;
  253. device_type = "pci";
  254. ranges = <0x81000000 0 0x00000000 0x30003000 0 0x00010000>,
  255. <0x82000000 0 0x30013000 0x30013000 0 0x0ffed000>;
  256. bus-range = <0x00 0xff>;
  257. #interrupt-cells = <1>;
  258. num-lanes = <1>;
  259. linux,pci-domain = <1>;
  260. phys = <&pcie2_phy>;
  261. phy-names = "pcie-phy0";
  262. interrupt-map-mask = <0 0 0 7>;
  263. interrupt-map = <0 0 0 1 &pcie2_intc 1>,
  264. <0 0 0 2 &pcie2_intc 2>,
  265. <0 0 0 3 &pcie2_intc 3>,
  266. <0 0 0 4 &pcie2_intc 4>;
  267. ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
  268. pcie2_intc: interrupt-controller {
  269. interrupt-controller;
  270. #address-cells = <0>;
  271. #interrupt-cells = <1>;
  272. };
  273. };
  274. };
  275. ocmcram1: ocmcram@40300000 {
  276. compatible = "mmio-sram";
  277. reg = <0x40300000 0x80000>;
  278. ranges = <0x0 0x40300000 0x80000>;
  279. #address-cells = <1>;
  280. #size-cells = <1>;
  281. /*
  282. * This is a placeholder for an optional reserved
  283. * region for use by secure software. The size
  284. * of this region is not known until runtime so it
  285. * is set as zero to either be updated to reserve
  286. * space or left unchanged to leave all SRAM for use.
  287. * On HS parts that that require the reserved region
  288. * either the bootloader can update the size to
  289. * the required amount or the node can be overridden
  290. * from the board dts file for the secure platform.
  291. */
  292. sram-hs@0 {
  293. compatible = "ti,secure-ram";
  294. reg = <0x0 0x0>;
  295. };
  296. };
  297. /*
  298. * NOTE: ocmcram2 and ocmcram3 are not available on all
  299. * DRA7xx and AM57xx variants. Confirm availability in
  300. * the data manual for the exact part number in use
  301. * before enabling these nodes in the board dts file.
  302. */
  303. ocmcram2: ocmcram@40400000 {
  304. status = "disabled";
  305. compatible = "mmio-sram";
  306. reg = <0x40400000 0x100000>;
  307. ranges = <0x0 0x40400000 0x100000>;
  308. #address-cells = <1>;
  309. #size-cells = <1>;
  310. };
  311. ocmcram3: ocmcram@40500000 {
  312. status = "disabled";
  313. compatible = "mmio-sram";
  314. reg = <0x40500000 0x100000>;
  315. ranges = <0x0 0x40500000 0x100000>;
  316. #address-cells = <1>;
  317. #size-cells = <1>;
  318. };
  319. bandgap: bandgap@4a0021e0 {
  320. reg = <0x4a0021e0 0xc
  321. 0x4a00232c 0xc
  322. 0x4a002380 0x2c
  323. 0x4a0023C0 0x3c
  324. 0x4a002564 0x8
  325. 0x4a002574 0x50>;
  326. compatible = "ti,dra752-bandgap";
  327. interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
  328. #thermal-sensor-cells = <1>;
  329. };
  330. dsp1_system: dsp_system@40d00000 {
  331. compatible = "syscon";
  332. reg = <0x40d00000 0x100>;
  333. };
  334. dra7_iodelay_core: padconf@4844a000 {
  335. compatible = "ti,dra7-iodelay";
  336. reg = <0x4844a000 0x0d1c>;
  337. #address-cells = <1>;
  338. #size-cells = <0>;
  339. #pinctrl-cells = <2>;
  340. };
  341. target-module@43300000 {
  342. compatible = "ti,sysc-omap4", "ti,sysc";
  343. reg = <0x43300000 0x4>,
  344. <0x43300010 0x4>;
  345. reg-names = "rev", "sysc";
  346. ti,sysc-midle = <SYSC_IDLE_FORCE>,
  347. <SYSC_IDLE_NO>,
  348. <SYSC_IDLE_SMART>;
  349. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  350. <SYSC_IDLE_NO>,
  351. <SYSC_IDLE_SMART>;
  352. clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPCC_CLKCTRL 0>;
  353. clock-names = "fck";
  354. #address-cells = <1>;
  355. #size-cells = <1>;
  356. ranges = <0x0 0x43300000 0x100000>;
  357. edma: dma@0 {
  358. compatible = "ti,edma3-tpcc";
  359. reg = <0 0x100000>;
  360. reg-names = "edma3_cc";
  361. interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
  362. <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
  363. <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
  364. interrupt-names = "edma3_ccint", "edma3_mperr",
  365. "edma3_ccerrint";
  366. dma-requests = <64>;
  367. #dma-cells = <2>;
  368. ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
  369. /*
  370. * memcpy is disabled, can be enabled with:
  371. * ti,edma-memcpy-channels = <20 21>;
  372. * for example. Note that these channels need to be
  373. * masked in the xbar as well.
  374. */
  375. };
  376. };
  377. target-module@43400000 {
  378. compatible = "ti,sysc-omap4", "ti,sysc";
  379. reg = <0x43400000 0x4>,
  380. <0x43400010 0x4>;
  381. reg-names = "rev", "sysc";
  382. ti,sysc-midle = <SYSC_IDLE_FORCE>,
  383. <SYSC_IDLE_NO>,
  384. <SYSC_IDLE_SMART>;
  385. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  386. <SYSC_IDLE_NO>,
  387. <SYSC_IDLE_SMART>;
  388. clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC0_CLKCTRL 0>;
  389. clock-names = "fck";
  390. #address-cells = <1>;
  391. #size-cells = <1>;
  392. ranges = <0x0 0x43400000 0x100000>;
  393. edma_tptc0: dma@0 {
  394. compatible = "ti,edma3-tptc";
  395. reg = <0 0x100000>;
  396. interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
  397. interrupt-names = "edma3_tcerrint";
  398. };
  399. };
  400. target-module@43500000 {
  401. compatible = "ti,sysc-omap4", "ti,sysc";
  402. reg = <0x43500000 0x4>,
  403. <0x43500010 0x4>;
  404. reg-names = "rev", "sysc";
  405. ti,sysc-midle = <SYSC_IDLE_FORCE>,
  406. <SYSC_IDLE_NO>,
  407. <SYSC_IDLE_SMART>;
  408. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  409. <SYSC_IDLE_NO>,
  410. <SYSC_IDLE_SMART>;
  411. clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC1_CLKCTRL 0>;
  412. clock-names = "fck";
  413. #address-cells = <1>;
  414. #size-cells = <1>;
  415. ranges = <0x0 0x43500000 0x100000>;
  416. edma_tptc1: dma@0 {
  417. compatible = "ti,edma3-tptc";
  418. reg = <0 0x100000>;
  419. interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
  420. interrupt-names = "edma3_tcerrint";
  421. };
  422. };
  423. target-module@4e000000 {
  424. compatible = "ti,sysc-omap2", "ti,sysc";
  425. reg = <0x4e000000 0x4>,
  426. <0x4e000010 0x4>;
  427. reg-names = "rev", "sysc";
  428. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  429. <SYSC_IDLE_NO>,
  430. <SYSC_IDLE_SMART>;
  431. ranges = <0x0 0x4e000000 0x2000000>;
  432. #size-cells = <1>;
  433. #address-cells = <1>;
  434. dmm@0 {
  435. compatible = "ti,omap5-dmm";
  436. reg = <0 0x800>;
  437. interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
  438. };
  439. };
  440. ipu1: ipu@58820000 {
  441. compatible = "ti,dra7-ipu";
  442. reg = <0x58820000 0x10000>;
  443. reg-names = "l2ram";
  444. iommus = <&mmu_ipu1>;
  445. status = "disabled";
  446. resets = <&prm_ipu 0>, <&prm_ipu 1>;
  447. clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>;
  448. firmware-name = "dra7-ipu1-fw.xem4";
  449. };
  450. ipu2: ipu@55020000 {
  451. compatible = "ti,dra7-ipu";
  452. reg = <0x55020000 0x10000>;
  453. reg-names = "l2ram";
  454. iommus = <&mmu_ipu2>;
  455. status = "disabled";
  456. resets = <&prm_core 0>, <&prm_core 1>;
  457. clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>;
  458. firmware-name = "dra7-ipu2-fw.xem4";
  459. };
  460. dsp1: dsp@40800000 {
  461. compatible = "ti,dra7-dsp";
  462. reg = <0x40800000 0x48000>,
  463. <0x40e00000 0x8000>,
  464. <0x40f00000 0x8000>;
  465. reg-names = "l2ram", "l1pram", "l1dram";
  466. ti,bootreg = <&scm_conf 0x55c 10>;
  467. iommus = <&mmu0_dsp1>, <&mmu1_dsp1>;
  468. status = "disabled";
  469. resets = <&prm_dsp1 0>;
  470. clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
  471. firmware-name = "dra7-dsp1-fw.xe66";
  472. };
  473. target-module@40d01000 {
  474. compatible = "ti,sysc-omap2", "ti,sysc";
  475. reg = <0x40d01000 0x4>,
  476. <0x40d01010 0x4>,
  477. <0x40d01014 0x4>;
  478. reg-names = "rev", "sysc", "syss";
  479. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  480. <SYSC_IDLE_NO>,
  481. <SYSC_IDLE_SMART>;
  482. ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
  483. SYSC_OMAP2_SOFTRESET |
  484. SYSC_OMAP2_AUTOIDLE)>;
  485. clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
  486. clock-names = "fck";
  487. resets = <&prm_dsp1 1>;
  488. reset-names = "rstctrl";
  489. ranges = <0x0 0x40d01000 0x1000>;
  490. #size-cells = <1>;
  491. #address-cells = <1>;
  492. mmu0_dsp1: mmu@0 {
  493. compatible = "ti,dra7-dsp-iommu";
  494. reg = <0x0 0x100>;
  495. interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
  496. #iommu-cells = <0>;
  497. ti,syscon-mmuconfig = <&dsp1_system 0x0>;
  498. };
  499. };
  500. target-module@40d02000 {
  501. compatible = "ti,sysc-omap2", "ti,sysc";
  502. reg = <0x40d02000 0x4>,
  503. <0x40d02010 0x4>,
  504. <0x40d02014 0x4>;
  505. reg-names = "rev", "sysc", "syss";
  506. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  507. <SYSC_IDLE_NO>,
  508. <SYSC_IDLE_SMART>;
  509. ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
  510. SYSC_OMAP2_SOFTRESET |
  511. SYSC_OMAP2_AUTOIDLE)>;
  512. clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
  513. clock-names = "fck";
  514. resets = <&prm_dsp1 1>;
  515. reset-names = "rstctrl";
  516. ranges = <0x0 0x40d02000 0x1000>;
  517. #size-cells = <1>;
  518. #address-cells = <1>;
  519. mmu1_dsp1: mmu@0 {
  520. compatible = "ti,dra7-dsp-iommu";
  521. reg = <0x0 0x100>;
  522. interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
  523. #iommu-cells = <0>;
  524. ti,syscon-mmuconfig = <&dsp1_system 0x1>;
  525. };
  526. };
  527. target-module@58882000 {
  528. compatible = "ti,sysc-omap2", "ti,sysc";
  529. reg = <0x58882000 0x4>,
  530. <0x58882010 0x4>,
  531. <0x58882014 0x4>;
  532. reg-names = "rev", "sysc", "syss";
  533. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  534. <SYSC_IDLE_NO>,
  535. <SYSC_IDLE_SMART>;
  536. ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
  537. SYSC_OMAP2_SOFTRESET |
  538. SYSC_OMAP2_AUTOIDLE)>;
  539. clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>;
  540. clock-names = "fck";
  541. resets = <&prm_ipu 2>;
  542. reset-names = "rstctrl";
  543. #address-cells = <1>;
  544. #size-cells = <1>;
  545. ranges = <0x0 0x58882000 0x100>;
  546. mmu_ipu1: mmu@0 {
  547. compatible = "ti,dra7-iommu";
  548. reg = <0x0 0x100>;
  549. interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
  550. #iommu-cells = <0>;
  551. ti,iommu-bus-err-back;
  552. };
  553. };
  554. target-module@55082000 {
  555. compatible = "ti,sysc-omap2", "ti,sysc";
  556. reg = <0x55082000 0x4>,
  557. <0x55082010 0x4>,
  558. <0x55082014 0x4>;
  559. reg-names = "rev", "sysc", "syss";
  560. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  561. <SYSC_IDLE_NO>,
  562. <SYSC_IDLE_SMART>;
  563. ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
  564. SYSC_OMAP2_SOFTRESET |
  565. SYSC_OMAP2_AUTOIDLE)>;
  566. clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>;
  567. clock-names = "fck";
  568. resets = <&prm_core 2>;
  569. reset-names = "rstctrl";
  570. #address-cells = <1>;
  571. #size-cells = <1>;
  572. ranges = <0x0 0x55082000 0x100>;
  573. mmu_ipu2: mmu@0 {
  574. compatible = "ti,dra7-iommu";
  575. reg = <0x0 0x100>;
  576. interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
  577. #iommu-cells = <0>;
  578. ti,iommu-bus-err-back;
  579. };
  580. };
  581. abb_mpu: regulator-abb-mpu {
  582. compatible = "ti,abb-v3";
  583. regulator-name = "abb_mpu";
  584. #address-cells = <0>;
  585. #size-cells = <0>;
  586. clocks = <&sys_clkin1>;
  587. ti,settling-time = <50>;
  588. ti,clock-cycles = <16>;
  589. reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
  590. <0x4ae06014 0x4>, <0x4a003b20 0xc>,
  591. <0x4ae0c158 0x4>;
  592. reg-names = "setup-address", "control-address",
  593. "int-address", "efuse-address",
  594. "ldo-address";
  595. ti,tranxdone-status-mask = <0x80>;
  596. /* LDOVBBMPU_FBB_MUX_CTRL */
  597. ti,ldovbb-override-mask = <0x400>;
  598. /* LDOVBBMPU_FBB_VSET_OUT */
  599. ti,ldovbb-vset-mask = <0x1F>;
  600. /*
  601. * NOTE: only FBB mode used but actual vset will
  602. * determine final biasing
  603. */
  604. ti,abb_info = <
  605. /*uV ABB efuse rbb_m fbb_m vset_m*/
  606. 1060000 0 0x0 0 0x02000000 0x01F00000
  607. 1160000 0 0x4 0 0x02000000 0x01F00000
  608. 1210000 0 0x8 0 0x02000000 0x01F00000
  609. >;
  610. };
  611. abb_ivahd: regulator-abb-ivahd {
  612. compatible = "ti,abb-v3";
  613. regulator-name = "abb_ivahd";
  614. #address-cells = <0>;
  615. #size-cells = <0>;
  616. clocks = <&sys_clkin1>;
  617. ti,settling-time = <50>;
  618. ti,clock-cycles = <16>;
  619. reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
  620. <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
  621. <0x4a002470 0x4>;
  622. reg-names = "setup-address", "control-address",
  623. "int-address", "efuse-address",
  624. "ldo-address";
  625. ti,tranxdone-status-mask = <0x40000000>;
  626. /* LDOVBBIVA_FBB_MUX_CTRL */
  627. ti,ldovbb-override-mask = <0x400>;
  628. /* LDOVBBIVA_FBB_VSET_OUT */
  629. ti,ldovbb-vset-mask = <0x1F>;
  630. /*
  631. * NOTE: only FBB mode used but actual vset will
  632. * determine final biasing
  633. */
  634. ti,abb_info = <
  635. /*uV ABB efuse rbb_m fbb_m vset_m*/
  636. 1055000 0 0x0 0 0x02000000 0x01F00000
  637. 1150000 0 0x4 0 0x02000000 0x01F00000
  638. 1250000 0 0x8 0 0x02000000 0x01F00000
  639. >;
  640. };
  641. abb_dspeve: regulator-abb-dspeve {
  642. compatible = "ti,abb-v3";
  643. regulator-name = "abb_dspeve";
  644. #address-cells = <0>;
  645. #size-cells = <0>;
  646. clocks = <&sys_clkin1>;
  647. ti,settling-time = <50>;
  648. ti,clock-cycles = <16>;
  649. reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
  650. <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
  651. <0x4a00246c 0x4>;
  652. reg-names = "setup-address", "control-address",
  653. "int-address", "efuse-address",
  654. "ldo-address";
  655. ti,tranxdone-status-mask = <0x20000000>;
  656. /* LDOVBBDSPEVE_FBB_MUX_CTRL */
  657. ti,ldovbb-override-mask = <0x400>;
  658. /* LDOVBBDSPEVE_FBB_VSET_OUT */
  659. ti,ldovbb-vset-mask = <0x1F>;
  660. /*
  661. * NOTE: only FBB mode used but actual vset will
  662. * determine final biasing
  663. */
  664. ti,abb_info = <
  665. /*uV ABB efuse rbb_m fbb_m vset_m*/
  666. 1055000 0 0x0 0 0x02000000 0x01F00000
  667. 1150000 0 0x4 0 0x02000000 0x01F00000
  668. 1250000 0 0x8 0 0x02000000 0x01F00000
  669. >;
  670. };
  671. abb_gpu: regulator-abb-gpu {
  672. compatible = "ti,abb-v3";
  673. regulator-name = "abb_gpu";
  674. #address-cells = <0>;
  675. #size-cells = <0>;
  676. clocks = <&sys_clkin1>;
  677. ti,settling-time = <50>;
  678. ti,clock-cycles = <16>;
  679. reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
  680. <0x4ae06010 0x4>, <0x4a003b08 0xc>,
  681. <0x4ae0c154 0x4>;
  682. reg-names = "setup-address", "control-address",
  683. "int-address", "efuse-address",
  684. "ldo-address";
  685. ti,tranxdone-status-mask = <0x10000000>;
  686. /* LDOVBBGPU_FBB_MUX_CTRL */
  687. ti,ldovbb-override-mask = <0x400>;
  688. /* LDOVBBGPU_FBB_VSET_OUT */
  689. ti,ldovbb-vset-mask = <0x1F>;
  690. /*
  691. * NOTE: only FBB mode used but actual vset will
  692. * determine final biasing
  693. */
  694. ti,abb_info = <
  695. /*uV ABB efuse rbb_m fbb_m vset_m*/
  696. 1090000 0 0x0 0 0x02000000 0x01F00000
  697. 1210000 0 0x4 0 0x02000000 0x01F00000
  698. 1280000 0 0x8 0 0x02000000 0x01F00000
  699. >;
  700. };
  701. target-module@4b300000 {
  702. compatible = "ti,sysc-omap4", "ti,sysc";
  703. reg = <0x4b300000 0x4>,
  704. <0x4b300010 0x4>;
  705. reg-names = "rev", "sysc";
  706. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  707. <SYSC_IDLE_NO>,
  708. <SYSC_IDLE_SMART>,
  709. <SYSC_IDLE_SMART_WKUP>;
  710. clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 0>;
  711. clock-names = "fck";
  712. #address-cells = <1>;
  713. #size-cells = <1>;
  714. ranges = <0x0 0x4b300000 0x1000>,
  715. <0x5c000000 0x5c000000 0x4000000>;
  716. qspi: spi@0 {
  717. compatible = "ti,dra7xxx-qspi";
  718. reg = <0 0x100>,
  719. <0x5c000000 0x4000000>;
  720. reg-names = "qspi_base", "qspi_mmap";
  721. syscon-chipselects = <&scm_conf 0x558>;
  722. #address-cells = <1>;
  723. #size-cells = <0>;
  724. clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 25>;
  725. clock-names = "fck";
  726. num-cs = <4>;
  727. interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
  728. status = "disabled";
  729. };
  730. };
  731. /* OCP2SCP1 */
  732. /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
  733. target-module@50000000 {
  734. compatible = "ti,sysc-omap2", "ti,sysc";
  735. reg = <0x50000000 4>,
  736. <0x50000010 4>,
  737. <0x50000014 4>;
  738. reg-names = "rev", "sysc", "syss";
  739. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  740. <SYSC_IDLE_NO>,
  741. <SYSC_IDLE_SMART>;
  742. ti,syss-mask = <1>;
  743. clocks = <&l3main1_clkctrl DRA7_L3MAIN1_GPMC_CLKCTRL 0>;
  744. clock-names = "fck";
  745. #address-cells = <1>;
  746. #size-cells = <1>;
  747. ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
  748. <0x00000000 0x00000000 0x40000000>; /* data */
  749. gpmc: gpmc@50000000 {
  750. compatible = "ti,am3352-gpmc";
  751. reg = <0x50000000 0x37c>; /* device IO registers */
  752. interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
  753. dmas = <&edma_xbar 4 0>;
  754. dma-names = "rxtx";
  755. gpmc,num-cs = <8>;
  756. gpmc,num-waitpins = <2>;
  757. #address-cells = <2>;
  758. #size-cells = <1>;
  759. interrupt-controller;
  760. #interrupt-cells = <2>;
  761. gpio-controller;
  762. #gpio-cells = <2>;
  763. status = "disabled";
  764. };
  765. };
  766. target-module@56000000 {
  767. compatible = "ti,sysc-omap4", "ti,sysc";
  768. reg = <0x5600fe00 0x4>,
  769. <0x5600fe10 0x4>;
  770. reg-names = "rev", "sysc";
  771. ti,sysc-midle = <SYSC_IDLE_FORCE>,
  772. <SYSC_IDLE_NO>,
  773. <SYSC_IDLE_SMART>;
  774. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  775. <SYSC_IDLE_NO>,
  776. <SYSC_IDLE_SMART>;
  777. clocks = <&gpu_clkctrl DRA7_GPU_CLKCTRL 0>;
  778. clock-names = "fck";
  779. #address-cells = <1>;
  780. #size-cells = <1>;
  781. ranges = <0 0x56000000 0x2000000>;
  782. };
  783. crossbar_mpu: crossbar@4a002a48 {
  784. compatible = "ti,irq-crossbar";
  785. reg = <0x4a002a48 0x130>;
  786. interrupt-controller;
  787. interrupt-parent = <&wakeupgen>;
  788. #interrupt-cells = <3>;
  789. ti,max-irqs = <160>;
  790. ti,max-crossbar-sources = <MAX_SOURCES>;
  791. ti,reg-size = <2>;
  792. ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
  793. ti,irqs-skip = <10 133 139 140>;
  794. ti,irqs-safe-map = <0>;
  795. };
  796. target-module@58000000 {
  797. compatible = "ti,sysc-omap2", "ti,sysc";
  798. reg = <0x58000000 4>,
  799. <0x58000014 4>;
  800. reg-names = "rev", "syss";
  801. ti,syss-mask = <1>;
  802. clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 0>,
  803. <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>,
  804. <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>,
  805. <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 11>;
  806. clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
  807. #address-cells = <1>;
  808. #size-cells = <1>;
  809. ranges = <0 0x58000000 0x800000>;
  810. dss: dss@0 {
  811. compatible = "ti,dra7-dss";
  812. /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
  813. /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
  814. status = "disabled";
  815. /* CTRL_CORE_DSS_PLL_CONTROL */
  816. syscon-pll-ctrl = <&scm_conf 0x538>;
  817. #address-cells = <1>;
  818. #size-cells = <1>;
  819. ranges = <0 0 0x800000>;
  820. target-module@1000 {
  821. compatible = "ti,sysc-omap2", "ti,sysc";
  822. reg = <0x1000 0x4>,
  823. <0x1010 0x4>,
  824. <0x1014 0x4>;
  825. reg-names = "rev", "sysc", "syss";
  826. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  827. <SYSC_IDLE_NO>,
  828. <SYSC_IDLE_SMART>;
  829. ti,sysc-midle = <SYSC_IDLE_FORCE>,
  830. <SYSC_IDLE_NO>,
  831. <SYSC_IDLE_SMART>;
  832. ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
  833. SYSC_OMAP2_ENAWAKEUP |
  834. SYSC_OMAP2_SOFTRESET |
  835. SYSC_OMAP2_AUTOIDLE)>;
  836. ti,syss-mask = <1>;
  837. clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>;
  838. clock-names = "fck";
  839. #address-cells = <1>;
  840. #size-cells = <1>;
  841. ranges = <0 0x1000 0x1000>;
  842. dispc@0 {
  843. compatible = "ti,dra7-dispc";
  844. reg = <0 0x1000>;
  845. interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
  846. clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>;
  847. clock-names = "fck";
  848. /* CTRL_CORE_SMA_SW_1 */
  849. syscon-pol = <&scm_conf 0x534>;
  850. };
  851. };
  852. target-module@40000 {
  853. compatible = "ti,sysc-omap4", "ti,sysc";
  854. reg = <0x40000 0x4>,
  855. <0x40010 0x4>;
  856. reg-names = "rev", "sysc";
  857. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  858. <SYSC_IDLE_NO>,
  859. <SYSC_IDLE_SMART>,
  860. <SYSC_IDLE_SMART_WKUP>;
  861. ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
  862. clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>,
  863. <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>;
  864. clock-names = "fck", "dss_clk";
  865. #address-cells = <1>;
  866. #size-cells = <1>;
  867. ranges = <0 0x40000 0x40000>;
  868. hdmi: encoder@0 {
  869. compatible = "ti,dra7-hdmi";
  870. reg = <0 0x200>,
  871. <0x200 0x80>,
  872. <0x300 0x80>,
  873. <0x20000 0x19000>;
  874. reg-names = "wp", "pll", "phy", "core";
  875. interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
  876. status = "disabled";
  877. clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>,
  878. <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>;
  879. clock-names = "fck", "sys_clk";
  880. dmas = <&sdma_xbar 76>;
  881. dma-names = "audio_tx";
  882. };
  883. };
  884. };
  885. };
  886. target-module@59000000 {
  887. compatible = "ti,sysc-omap4", "ti,sysc";
  888. reg = <0x59000020 0x4>;
  889. reg-names = "rev";
  890. clocks = <&dss_clkctrl DRA7_DSS_BB2D_CLKCTRL 0>;
  891. clock-names = "fck";
  892. #address-cells = <1>;
  893. #size-cells = <1>;
  894. ranges = <0x0 0x59000000 0x1000>;
  895. bb2d: gpu@0 {
  896. compatible = "vivante,gc";
  897. reg = <0x0 0x700>;
  898. interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
  899. clocks = <&dss_clkctrl DRA7_DSS_BB2D_CLKCTRL 0>;
  900. clock-names = "core";
  901. };
  902. };
  903. aes1_target: target-module@4b500000 {
  904. compatible = "ti,sysc-omap2", "ti,sysc";
  905. reg = <0x4b500080 0x4>,
  906. <0x4b500084 0x4>,
  907. <0x4b500088 0x4>;
  908. reg-names = "rev", "sysc", "syss";
  909. ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
  910. SYSC_OMAP2_AUTOIDLE)>;
  911. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  912. <SYSC_IDLE_NO>,
  913. <SYSC_IDLE_SMART>,
  914. <SYSC_IDLE_SMART_WKUP>;
  915. ti,syss-mask = <1>;
  916. /* Domains (P, C): per_pwrdm, l4sec_clkdm */
  917. clocks = <&l4sec_clkctrl DRA7_L4SEC_AES1_CLKCTRL 0>;
  918. clock-names = "fck";
  919. #address-cells = <1>;
  920. #size-cells = <1>;
  921. ranges = <0x0 0x4b500000 0x1000>;
  922. aes1: aes@0 {
  923. compatible = "ti,omap4-aes";
  924. reg = <0 0xa0>;
  925. interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
  926. dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
  927. dma-names = "tx", "rx";
  928. clocks = <&l3_iclk_div>;
  929. clock-names = "fck";
  930. };
  931. };
  932. aes2_target: target-module@4b700000 {
  933. compatible = "ti,sysc-omap2", "ti,sysc";
  934. reg = <0x4b700080 0x4>,
  935. <0x4b700084 0x4>,
  936. <0x4b700088 0x4>;
  937. reg-names = "rev", "sysc", "syss";
  938. ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
  939. SYSC_OMAP2_AUTOIDLE)>;
  940. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  941. <SYSC_IDLE_NO>,
  942. <SYSC_IDLE_SMART>,
  943. <SYSC_IDLE_SMART_WKUP>;
  944. ti,syss-mask = <1>;
  945. /* Domains (P, C): per_pwrdm, l4sec_clkdm */
  946. clocks = <&l4sec_clkctrl DRA7_L4SEC_AES2_CLKCTRL 0>;
  947. clock-names = "fck";
  948. #address-cells = <1>;
  949. #size-cells = <1>;
  950. ranges = <0x0 0x4b700000 0x1000>;
  951. aes2: aes@0 {
  952. compatible = "ti,omap4-aes";
  953. reg = <0 0xa0>;
  954. interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
  955. dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
  956. dma-names = "tx", "rx";
  957. clocks = <&l3_iclk_div>;
  958. clock-names = "fck";
  959. };
  960. };
  961. sham1_target: target-module@4b101000 {
  962. compatible = "ti,sysc-omap3-sham", "ti,sysc";
  963. reg = <0x4b101100 0x4>,
  964. <0x4b101110 0x4>,
  965. <0x4b101114 0x4>;
  966. reg-names = "rev", "sysc", "syss";
  967. ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
  968. SYSC_OMAP2_AUTOIDLE)>;
  969. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  970. <SYSC_IDLE_NO>,
  971. <SYSC_IDLE_SMART>;
  972. ti,syss-mask = <1>;
  973. /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
  974. clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM_CLKCTRL 0>;
  975. clock-names = "fck";
  976. #address-cells = <1>;
  977. #size-cells = <1>;
  978. ranges = <0x0 0x4b101000 0x1000>;
  979. sham1: sham@0 {
  980. compatible = "ti,omap5-sham";
  981. reg = <0 0x300>;
  982. interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
  983. dmas = <&edma_xbar 119 0>;
  984. dma-names = "rx";
  985. clocks = <&l3_iclk_div>;
  986. clock-names = "fck";
  987. };
  988. };
  989. sham2_target: target-module@42701000 {
  990. compatible = "ti,sysc-omap3-sham", "ti,sysc";
  991. reg = <0x42701100 0x4>,
  992. <0x42701110 0x4>,
  993. <0x42701114 0x4>;
  994. reg-names = "rev", "sysc", "syss";
  995. ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
  996. SYSC_OMAP2_AUTOIDLE)>;
  997. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  998. <SYSC_IDLE_NO>,
  999. <SYSC_IDLE_SMART>;
  1000. ti,syss-mask = <1>;
  1001. /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
  1002. clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM2_CLKCTRL 0>;
  1003. clock-names = "fck";
  1004. #address-cells = <1>;
  1005. #size-cells = <1>;
  1006. ranges = <0x0 0x42701000 0x1000>;
  1007. sham2: sham@0 {
  1008. compatible = "ti,omap5-sham";
  1009. reg = <0 0x300>;
  1010. interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
  1011. dmas = <&edma_xbar 165 0>;
  1012. dma-names = "rx";
  1013. clocks = <&l3_iclk_div>;
  1014. clock-names = "fck";
  1015. };
  1016. };
  1017. iva_hd_target: target-module@5a000000 {
  1018. compatible = "ti,sysc-omap4", "ti,sysc";
  1019. reg = <0x5a05a400 0x4>,
  1020. <0x5a05a410 0x4>;
  1021. reg-names = "rev", "sysc";
  1022. ti,sysc-midle = <SYSC_IDLE_FORCE>,
  1023. <SYSC_IDLE_NO>,
  1024. <SYSC_IDLE_SMART>;
  1025. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  1026. <SYSC_IDLE_NO>,
  1027. <SYSC_IDLE_SMART>;
  1028. power-domains = <&prm_iva>;
  1029. resets = <&prm_iva 2>;
  1030. reset-names = "rstctrl";
  1031. clocks = <&iva_clkctrl DRA7_IVA_CLKCTRL 0>;
  1032. clock-names = "fck";
  1033. #address-cells = <1>;
  1034. #size-cells = <1>;
  1035. ranges = <0x5a000000 0x5a000000 0x1000000>,
  1036. <0x5b000000 0x5b000000 0x1000000>;
  1037. iva {
  1038. compatible = "ti,ivahd";
  1039. };
  1040. };
  1041. opp_supply_mpu: opp-supply@4a003b20 {
  1042. compatible = "ti,omap5-opp-supply";
  1043. reg = <0x4a003b20 0xc>;
  1044. ti,efuse-settings = <
  1045. /* uV offset */
  1046. 1060000 0x0
  1047. 1160000 0x4
  1048. 1210000 0x8
  1049. >;
  1050. ti,absolute-max-voltage-uv = <1500000>;
  1051. };
  1052. };
  1053. thermal_zones: thermal-zones {
  1054. #include "omap4-cpu-thermal.dtsi"
  1055. #include "omap5-gpu-thermal.dtsi"
  1056. #include "omap5-core-thermal.dtsi"
  1057. #include "dra7-dspeve-thermal.dtsi"
  1058. #include "dra7-iva-thermal.dtsi"
  1059. };
  1060. };
  1061. &cpu_thermal {
  1062. polling-delay = <500>; /* milliseconds */
  1063. coefficients = <0 2000>;
  1064. };
  1065. &gpu_thermal {
  1066. coefficients = <0 2000>;
  1067. };
  1068. &core_thermal {
  1069. coefficients = <0 2000>;
  1070. };
  1071. &dspeve_thermal {
  1072. coefficients = <0 2000>;
  1073. };
  1074. &iva_thermal {
  1075. coefficients = <0 2000>;
  1076. };
  1077. &cpu_crit {
  1078. temperature = <120000>; /* milli Celsius */
  1079. };
  1080. &core_crit {
  1081. temperature = <120000>; /* milli Celsius */
  1082. };
  1083. &gpu_crit {
  1084. temperature = <120000>; /* milli Celsius */
  1085. };
  1086. &dspeve_crit {
  1087. temperature = <120000>; /* milli Celsius */
  1088. };
  1089. &iva_crit {
  1090. temperature = <120000>; /* milli Celsius */
  1091. };
  1092. #include "dra7-l4.dtsi"
  1093. #include "dra7xx-clocks.dtsi"
  1094. &prm {
  1095. prm_mpu: prm@300 {
  1096. compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
  1097. reg = <0x300 0x100>;
  1098. #power-domain-cells = <0>;
  1099. };
  1100. prm_dsp1: prm@400 {
  1101. compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
  1102. reg = <0x400 0x100>;
  1103. #reset-cells = <1>;
  1104. #power-domain-cells = <0>;
  1105. };
  1106. prm_ipu: prm@500 {
  1107. compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
  1108. reg = <0x500 0x100>;
  1109. #reset-cells = <1>;
  1110. #power-domain-cells = <0>;
  1111. };
  1112. prm_coreaon: prm@628 {
  1113. compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
  1114. reg = <0x628 0xd8>;
  1115. #power-domain-cells = <0>;
  1116. };
  1117. prm_core: prm@700 {
  1118. compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
  1119. reg = <0x700 0x100>;
  1120. #reset-cells = <1>;
  1121. #power-domain-cells = <0>;
  1122. };
  1123. prm_iva: prm@f00 {
  1124. compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
  1125. reg = <0xf00 0x100>;
  1126. #reset-cells = <1>;
  1127. #power-domain-cells = <0>;
  1128. };
  1129. prm_cam: prm@1000 {
  1130. compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
  1131. reg = <0x1000 0x100>;
  1132. #power-domain-cells = <0>;
  1133. };
  1134. prm_dss: prm@1100 {
  1135. compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
  1136. reg = <0x1100 0x100>;
  1137. #power-domain-cells = <0>;
  1138. };
  1139. prm_gpu: prm@1200 {
  1140. compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
  1141. reg = <0x1200 0x100>;
  1142. #power-domain-cells = <0>;
  1143. };
  1144. prm_l3init: prm@1300 {
  1145. compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
  1146. reg = <0x1300 0x100>;
  1147. #reset-cells = <1>;
  1148. #power-domain-cells = <0>;
  1149. };
  1150. prm_l4per: prm@1400 {
  1151. compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
  1152. reg = <0x1400 0x100>;
  1153. #power-domain-cells = <0>;
  1154. };
  1155. prm_custefuse: prm@1600 {
  1156. compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
  1157. reg = <0x1600 0x100>;
  1158. #power-domain-cells = <0>;
  1159. };
  1160. prm_wkupaon: prm@1724 {
  1161. compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
  1162. reg = <0x1724 0x100>;
  1163. #power-domain-cells = <0>;
  1164. };
  1165. prm_dsp2: prm@1b00 {
  1166. compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
  1167. reg = <0x1b00 0x40>;
  1168. #reset-cells = <1>;
  1169. #power-domain-cells = <0>;
  1170. };
  1171. prm_eve1: prm@1b40 {
  1172. compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
  1173. reg = <0x1b40 0x40>;
  1174. #power-domain-cells = <0>;
  1175. };
  1176. prm_eve2: prm@1b80 {
  1177. compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
  1178. reg = <0x1b80 0x40>;
  1179. #power-domain-cells = <0>;
  1180. };
  1181. prm_eve3: prm@1bc0 {
  1182. compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
  1183. reg = <0x1bc0 0x40>;
  1184. #power-domain-cells = <0>;
  1185. };
  1186. prm_eve4: prm@1c00 {
  1187. compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
  1188. reg = <0x1c00 0x60>;
  1189. #power-domain-cells = <0>;
  1190. };
  1191. prm_rtc: prm@1c60 {
  1192. compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
  1193. reg = <0x1c60 0x20>;
  1194. #power-domain-cells = <0>;
  1195. };
  1196. prm_vpe: prm@1c80 {
  1197. compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
  1198. reg = <0x1c80 0x80>;
  1199. #power-domain-cells = <0>;
  1200. };
  1201. };
  1202. /* Preferred always-on timer for clockevent */
  1203. &timer1_target {
  1204. ti,no-reset-on-init;
  1205. ti,no-idle;
  1206. timer@0 {
  1207. assigned-clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 24>;
  1208. assigned-clock-parents = <&sys_32k_ck>;
  1209. };
  1210. };
  1211. /* Local timers, see ARM architected timer wrap erratum i940 */
  1212. &timer15_target {
  1213. ti,no-reset-on-init;
  1214. ti,no-idle;
  1215. timer@0 {
  1216. assigned-clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>;
  1217. assigned-clock-parents = <&timer_sys_clk_div>;
  1218. };
  1219. };
  1220. &timer16_target {
  1221. ti,no-reset-on-init;
  1222. ti,no-idle;
  1223. timer@0 {
  1224. assigned-clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>;
  1225. assigned-clock-parents = <&timer_sys_clk_div>;
  1226. };
  1227. };