dm8168-evm.dts 5.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /dts-v1/;
  3. #include "dm816x.dtsi"
  4. #include <dt-bindings/interrupt-controller/irq.h>
  5. / {
  6. model = "DM8168 EVM";
  7. compatible = "ti,dm8168-evm", "ti,dm8168", "ti,dm816";
  8. memory@80000000 {
  9. device_type = "memory";
  10. reg = <0x80000000 0x40000000 /* 1 GB */
  11. 0xc0000000 0x40000000>; /* 1 GB */
  12. };
  13. /* FDC6331L controlled by SD_POW pin */
  14. vmmcsd_fixed: fixedregulator0 {
  15. compatible = "regulator-fixed";
  16. regulator-name = "vmmcsd_fixed";
  17. regulator-min-microvolt = <3300000>;
  18. regulator-max-microvolt = <3300000>;
  19. };
  20. sata_refclk: fixedclock0 {
  21. compatible = "fixed-clock";
  22. #clock-cells = <0>;
  23. clock-frequency = <100000000>;
  24. };
  25. };
  26. &dm816x_pinmux {
  27. mcspi1_pins: pinmux_mcspi1_pins {
  28. pinctrl-single,pins = <
  29. DM816X_IOPAD(0x0a94, MUX_MODE0) /* SPI_SCLK */
  30. DM816X_IOPAD(0x0a98, MUX_MODE0) /* SPI_SCS0 */
  31. DM816X_IOPAD(0x0aa8, MUX_MODE0) /* SPI_D0 */
  32. DM816X_IOPAD(0x0aac, MUX_MODE0) /* SPI_D1 */
  33. >;
  34. };
  35. mmc_pins: pinmux_mmc_pins {
  36. pinctrl-single,pins = <
  37. DM816X_IOPAD(0x0a70, MUX_MODE0) /* SD_POW */
  38. DM816X_IOPAD(0x0a74, MUX_MODE0) /* SD_CLK */
  39. DM816X_IOPAD(0x0a78, MUX_MODE0) /* SD_CMD */
  40. DM816X_IOPAD(0x0a7C, MUX_MODE0) /* SD_DAT0 */
  41. DM816X_IOPAD(0x0a80, MUX_MODE0) /* SD_DAT1 */
  42. DM816X_IOPAD(0x0a84, MUX_MODE0) /* SD_DAT2 */
  43. DM816X_IOPAD(0x0a88, MUX_MODE0) /* SD_DAT2 */
  44. DM816X_IOPAD(0x0a8c, MUX_MODE2) /* GP1[7] */
  45. DM816X_IOPAD(0x0a90, MUX_MODE2) /* GP1[8] */
  46. >;
  47. };
  48. usb0_pins: pinmux_usb0_pins {
  49. pinctrl-single,pins = <
  50. DM816X_IOPAD(0x0d04, MUX_MODE0) /* USB0_DRVVBUS */
  51. >;
  52. };
  53. usb1_pins: pinmux_usb1_pins {
  54. pinctrl-single,pins = <
  55. DM816X_IOPAD(0x0d08, MUX_MODE0) /* USB1_DRVVBUS */
  56. >;
  57. };
  58. nandflash_pins: nandflash_pins {
  59. pinctrl-single,pins = <
  60. DM816X_IOPAD(0x0b38, PULL_UP | MUX_MODE0) /* PINCTRL207 GPMC_CS0*/
  61. DM816X_IOPAD(0x0b60, PULL_ENA | MUX_MODE0) /* PINCTRL217 GPMC_ADV_ALE */
  62. DM816X_IOPAD(0x0b54, PULL_UP | PULL_ENA | MUX_MODE0) /* PINCTRL214 GPMC_OE_RE */
  63. DM816X_IOPAD(0x0b58, PULL_ENA | MUX_MODE0) /* PINCTRL215 GPMC_BE0_CLE */
  64. DM816X_IOPAD(0x0b50, PULL_UP | MUX_MODE0) /* PINCTRL213 GPMC_WE */
  65. DM816X_IOPAD(0x0b6c, MUX_MODE0) /* PINCTRL220 GPMC_WAIT */
  66. DM816X_IOPAD(0x0be4, PULL_ENA | MUX_MODE0) /* PINCTRL250 GPMC_CLK */
  67. DM816X_IOPAD(0x0ba4, MUX_MODE0) /* PINCTRL234 GPMC_D0 */
  68. DM816X_IOPAD(0x0ba8, MUX_MODE0) /* PINCTRL234 GPMC_D1 */
  69. DM816X_IOPAD(0x0bac, MUX_MODE0) /* PINCTRL234 GPMC_D2 */
  70. DM816X_IOPAD(0x0bb0, MUX_MODE0) /* PINCTRL234 GPMC_D3 */
  71. DM816X_IOPAD(0x0bb4, MUX_MODE0) /* PINCTRL234 GPMC_D4 */
  72. DM816X_IOPAD(0x0bb8, MUX_MODE0) /* PINCTRL234 GPMC_D5 */
  73. DM816X_IOPAD(0x0bbc, MUX_MODE0) /* PINCTRL234 GPMC_D6 */
  74. DM816X_IOPAD(0x0bc0, MUX_MODE0) /* PINCTRL234 GPMC_D7 */
  75. DM816X_IOPAD(0x0bc4, MUX_MODE0) /* PINCTRL234 GPMC_D8 */
  76. DM816X_IOPAD(0x0bc8, MUX_MODE0) /* PINCTRL234 GPMC_D9 */
  77. DM816X_IOPAD(0x0bcc, MUX_MODE0) /* PINCTRL234 GPMC_D10 */
  78. DM816X_IOPAD(0x0bd0, MUX_MODE0) /* PINCTRL234 GPMC_D11 */
  79. DM816X_IOPAD(0x0bd4, MUX_MODE0) /* PINCTRL234 GPMC_D12 */
  80. DM816X_IOPAD(0x0bd8, MUX_MODE0) /* PINCTRL234 GPMC_D13 */
  81. DM816X_IOPAD(0x0bdc, MUX_MODE0) /* PINCTRL234 GPMC_D14 */
  82. DM816X_IOPAD(0x0be0, MUX_MODE0) /* PINCTRL234 GPMC_D15 */
  83. >;
  84. };
  85. };
  86. &i2c1 {
  87. extgpio0: pcf8575@20 {
  88. compatible = "nxp,pcf8575";
  89. reg = <0x20>;
  90. gpio-controller;
  91. #gpio-cells = <2>;
  92. };
  93. };
  94. &i2c2 {
  95. extgpio1: pcf8575@20 {
  96. compatible = "nxp,pcf8575";
  97. reg = <0x20>;
  98. gpio-controller;
  99. #gpio-cells = <2>;
  100. };
  101. };
  102. &gpmc {
  103. ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */
  104. pinctrl-names = "default";
  105. pinctrl-0 = <&nandflash_pins>;
  106. nand@0,0 {
  107. compatible = "ti,omap2-nand";
  108. linux,mtd-name = "micron,mt29f2g16aadwp";
  109. reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
  110. interrupt-parent = <&gpmc>;
  111. interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
  112. <1 IRQ_TYPE_NONE>; /* termcount */
  113. rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
  114. #address-cells = <1>;
  115. #size-cells = <1>;
  116. ti,nand-ecc-opt = "bch8";
  117. ti,elm-id = <&elm>;
  118. nand-bus-width = <16>;
  119. gpmc,device-width = <2>;
  120. gpmc,sync-clk-ps = <0>;
  121. gpmc,cs-on-ns = <0>;
  122. gpmc,cs-rd-off-ns = <44>;
  123. gpmc,cs-wr-off-ns = <44>;
  124. gpmc,adv-on-ns = <6>;
  125. gpmc,adv-rd-off-ns = <34>;
  126. gpmc,adv-wr-off-ns = <44>;
  127. gpmc,we-on-ns = <0>;
  128. gpmc,we-off-ns = <40>;
  129. gpmc,oe-on-ns = <0>;
  130. gpmc,oe-off-ns = <54>;
  131. gpmc,access-ns = <64>;
  132. gpmc,rd-cycle-ns = <82>;
  133. gpmc,wr-cycle-ns = <82>;
  134. gpmc,bus-turnaround-ns = <0>;
  135. gpmc,cycle2cycle-delay-ns = <0>;
  136. gpmc,clk-activation-ns = <0>;
  137. gpmc,wr-access-ns = <40>;
  138. gpmc,wr-data-mux-bus-ns = <0>;
  139. partition@0 {
  140. label = "X-Loader";
  141. reg = <0 0x80000>;
  142. };
  143. partition@80000 {
  144. label = "U-Boot";
  145. reg = <0x80000 0x1c0000>;
  146. };
  147. partition@1c0000 {
  148. label = "Environment";
  149. reg = <0x240000 0x40000>;
  150. };
  151. partition@280000 {
  152. label = "Kernel";
  153. reg = <0x280000 0x500000>;
  154. };
  155. partition@780000 {
  156. label = "Filesystem";
  157. reg = <0x780000 0xf880000>;
  158. };
  159. };
  160. };
  161. &mcspi1 {
  162. pinctrl-names = "default";
  163. pinctrl-0 = <&mcspi1_pins>;
  164. flash@0 {
  165. compatible = "w25x32";
  166. spi-max-frequency = <48000000>;
  167. reg = <0>;
  168. #address-cells = <1>;
  169. #size-cells = <1>;
  170. };
  171. };
  172. &mmc1 {
  173. pinctrl-names = "default";
  174. pinctrl-0 = <&mmc_pins>;
  175. vmmc-supply = <&vmmcsd_fixed>;
  176. bus-width = <4>;
  177. cd-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
  178. wp-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
  179. };
  180. /* At least dm8168-evm rev c won't support multipoint, later may */
  181. &usb0 {
  182. pinctrl-names = "default";
  183. pinctrl-0 = <&usb0_pins>;
  184. mentor,multipoint = <0>;
  185. };
  186. &usb1 {
  187. pinctrl-names = "default";
  188. pinctrl-0 = <&usb1_pins>;
  189. mentor,multipoint = <0>;
  190. };
  191. &sata {
  192. clocks = <&sysclk5_ck>, <&sata_refclk>;
  193. };