bcm53573.dtsi 4.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. /*
  3. * Copyright (C) 2016 Rafał Miłecki <[email protected]>
  4. */
  5. #include <dt-bindings/gpio/gpio.h>
  6. #include <dt-bindings/input/input.h>
  7. #include <dt-bindings/interrupt-controller/irq.h>
  8. #include <dt-bindings/interrupt-controller/arm-gic.h>
  9. / {
  10. #address-cells = <1>;
  11. #size-cells = <1>;
  12. interrupt-parent = <&gic>;
  13. aliases {
  14. serial0 = &uart0;
  15. };
  16. chosen {
  17. stdout-path = "serial0:115200n8";
  18. };
  19. cpus {
  20. #address-cells = <1>;
  21. #size-cells = <0>;
  22. cpu@0 {
  23. device_type = "cpu";
  24. compatible = "arm,cortex-a7";
  25. reg = <0x0>;
  26. };
  27. };
  28. mpcore@18310000 {
  29. compatible = "simple-bus";
  30. ranges = <0x00000000 0x18310000 0x00008000>;
  31. #address-cells = <1>;
  32. #size-cells = <1>;
  33. gic: interrupt-controller@1000 {
  34. compatible = "arm,cortex-a7-gic";
  35. #interrupt-cells = <3>;
  36. #address-cells = <0>;
  37. interrupt-controller;
  38. reg = <0x1000 0x1000>,
  39. <0x2000 0x0100>;
  40. };
  41. };
  42. timer {
  43. compatible = "arm,armv7-timer";
  44. interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
  45. <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
  46. <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
  47. <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
  48. };
  49. clocks {
  50. #address-cells = <1>;
  51. #size-cells = <1>;
  52. ranges;
  53. alp: oscillator {
  54. #clock-cells = <0>;
  55. compatible = "fixed-clock";
  56. clock-frequency = <40000000>;
  57. };
  58. };
  59. axi@18000000 {
  60. compatible = "brcm,bus-axi";
  61. reg = <0x18000000 0x1000>;
  62. ranges = <0x00000000 0x18000000 0x00100000>;
  63. #address-cells = <1>;
  64. #size-cells = <1>;
  65. #interrupt-cells = <1>;
  66. interrupt-map-mask = <0x000fffff 0xffff>;
  67. interrupt-map =
  68. /* ChipCommon */
  69. <0x00000000 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  70. /* IEEE 802.11 0 */
  71. <0x00001000 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
  72. /* PCIe Controller 0 */
  73. <0x00002000 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
  74. <0x00002000 1 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
  75. <0x00002000 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
  76. <0x00002000 3 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
  77. <0x00002000 4 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
  78. <0x00002000 5 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
  79. /* USB 2.0 Controller */
  80. <0x00004000 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
  81. /* Ethernet Controller 0 */
  82. <0x00005000 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
  83. /* IEEE 802.11 1 */
  84. <0x0000a000 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
  85. /* Ethernet Controller 1 */
  86. <0x0000b000 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
  87. chipcommon: chipcommon@0 {
  88. compatible = "simple-bus";
  89. reg = <0x00000000 0x1000>;
  90. ranges;
  91. #address-cells = <1>;
  92. #size-cells = <1>;
  93. gpio-controller;
  94. #gpio-cells = <2>;
  95. uart0: serial@300 {
  96. compatible = "ns16550a";
  97. reg = <0x0300 0x100>;
  98. interrupt-parent = <&gic>;
  99. interrupts = <GIC_PPI 16 IRQ_TYPE_LEVEL_HIGH>;
  100. clocks = <&alp>;
  101. status = "okay";
  102. };
  103. };
  104. pcie0: pcie@2000 {
  105. reg = <0x00002000 0x1000>;
  106. #address-cells = <3>;
  107. #size-cells = <2>;
  108. };
  109. usb2: usb2@4000 {
  110. reg = <0x4000 0x1000>;
  111. ranges;
  112. #address-cells = <1>;
  113. #size-cells = <1>;
  114. ehci: usb@4000 {
  115. compatible = "generic-ehci";
  116. reg = <0x4000 0x1000>;
  117. interrupt-parent = <&gic>;
  118. interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
  119. #address-cells = <1>;
  120. #size-cells = <0>;
  121. ehci_port1: port@1 {
  122. reg = <1>;
  123. #trigger-source-cells = <0>;
  124. };
  125. ehci_port2: port@2 {
  126. reg = <2>;
  127. #trigger-source-cells = <0>;
  128. };
  129. };
  130. ohci: usb@d000 {
  131. compatible = "generic-ohci";
  132. reg = <0xd000 0x1000>;
  133. interrupt-parent = <&gic>;
  134. interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
  135. #address-cells = <1>;
  136. #size-cells = <0>;
  137. ohci_port1: port@1 {
  138. reg = <1>;
  139. #trigger-source-cells = <0>;
  140. };
  141. ohci_port2: port@2 {
  142. reg = <2>;
  143. #trigger-source-cells = <0>;
  144. };
  145. };
  146. };
  147. gmac0: ethernet@5000 {
  148. reg = <0x5000 0x1000>;
  149. mdio {
  150. #address-cells = <1>;
  151. #size-cells = <0>;
  152. switch: switch@1e {
  153. compatible = "brcm,bcm53125";
  154. reg = <0x1e>;
  155. status = "disabled";
  156. /* ports are defined in board DTS */
  157. ports {
  158. #address-cells = <1>;
  159. #size-cells = <0>;
  160. };
  161. };
  162. };
  163. };
  164. gmac1: ethernet@b000 {
  165. reg = <0xb000 0x1000>;
  166. };
  167. pmu@12000 {
  168. compatible = "simple-mfd", "syscon";
  169. reg = <0x00012000 0x00001000>;
  170. ilp: ilp {
  171. compatible = "brcm,bcm53573-ilp";
  172. clocks = <&alp>;
  173. #clock-cells = <0>;
  174. clock-output-names = "ilp";
  175. };
  176. };
  177. };
  178. };