bcm2835-common.dtsi 4.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208
  1. // SPDX-License-Identifier: GPL-2.0
  2. /* This include file covers the common peripherals and configuration between
  3. * bcm2835, bcm2836 and bcm2837 implementations.
  4. */
  5. / {
  6. interrupt-parent = <&intc>;
  7. soc {
  8. dma: dma@7e007000 {
  9. compatible = "brcm,bcm2835-dma";
  10. reg = <0x7e007000 0xf00>;
  11. interrupts = <1 16>,
  12. <1 17>,
  13. <1 18>,
  14. <1 19>,
  15. <1 20>,
  16. <1 21>,
  17. <1 22>,
  18. <1 23>,
  19. <1 24>,
  20. <1 25>,
  21. <1 26>,
  22. /* dma channel 11-14 share one irq */
  23. <1 27>,
  24. <1 27>,
  25. <1 27>,
  26. <1 27>,
  27. /* unused shared irq for all channels */
  28. <1 28>;
  29. interrupt-names = "dma0",
  30. "dma1",
  31. "dma2",
  32. "dma3",
  33. "dma4",
  34. "dma5",
  35. "dma6",
  36. "dma7",
  37. "dma8",
  38. "dma9",
  39. "dma10",
  40. "dma11",
  41. "dma12",
  42. "dma13",
  43. "dma14",
  44. "dma-shared-all";
  45. #dma-cells = <1>;
  46. brcm,dma-channel-mask = <0x7f35>;
  47. };
  48. intc: interrupt-controller@7e00b200 {
  49. compatible = "brcm,bcm2835-armctrl-ic";
  50. reg = <0x7e00b200 0x200>;
  51. interrupt-controller;
  52. #interrupt-cells = <2>;
  53. };
  54. pm: watchdog@7e100000 {
  55. compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt";
  56. #power-domain-cells = <1>;
  57. #reset-cells = <1>;
  58. reg = <0x7e100000 0x114>,
  59. <0x7e00a000 0x24>;
  60. reg-names = "pm", "asb";
  61. clocks = <&clocks BCM2835_CLOCK_V3D>,
  62. <&clocks BCM2835_CLOCK_PERI_IMAGE>,
  63. <&clocks BCM2835_CLOCK_H264>,
  64. <&clocks BCM2835_CLOCK_ISP>;
  65. clock-names = "v3d", "peri_image", "h264", "isp";
  66. system-power-controller;
  67. };
  68. rng@7e104000 {
  69. compatible = "brcm,bcm2835-rng";
  70. reg = <0x7e104000 0x10>;
  71. interrupts = <2 29>;
  72. };
  73. pixelvalve@7e206000 {
  74. compatible = "brcm,bcm2835-pixelvalve0";
  75. reg = <0x7e206000 0x100>;
  76. interrupts = <2 13>; /* pwa0 */
  77. };
  78. pixelvalve@7e207000 {
  79. compatible = "brcm,bcm2835-pixelvalve1";
  80. reg = <0x7e207000 0x100>;
  81. interrupts = <2 14>; /* pwa1 */
  82. };
  83. thermal: thermal@7e212000 {
  84. compatible = "brcm,bcm2835-thermal";
  85. reg = <0x7e212000 0x8>;
  86. clocks = <&clocks BCM2835_CLOCK_TSENS>;
  87. #thermal-sensor-cells = <0>;
  88. status = "disabled";
  89. };
  90. i2c2: i2c@7e805000 {
  91. compatible = "brcm,bcm2835-i2c";
  92. reg = <0x7e805000 0x1000>;
  93. interrupts = <2 21>;
  94. clocks = <&clocks BCM2835_CLOCK_VPU>;
  95. #address-cells = <1>;
  96. #size-cells = <0>;
  97. status = "okay";
  98. };
  99. vec: vec@7e806000 {
  100. compatible = "brcm,bcm2835-vec";
  101. reg = <0x7e806000 0x1000>;
  102. clocks = <&clocks BCM2835_CLOCK_VEC>;
  103. interrupts = <2 27>;
  104. status = "disabled";
  105. };
  106. pixelvalve@7e807000 {
  107. compatible = "brcm,bcm2835-pixelvalve2";
  108. reg = <0x7e807000 0x100>;
  109. interrupts = <2 10>; /* pixelvalve */
  110. };
  111. hdmi: hdmi@7e902000 {
  112. compatible = "brcm,bcm2835-hdmi";
  113. reg = <0x7e902000 0x600>,
  114. <0x7e808000 0x100>;
  115. interrupts = <2 8>, <2 9>;
  116. ddc = <&i2c2>;
  117. clocks = <&clocks BCM2835_PLLH_PIX>,
  118. <&clocks BCM2835_CLOCK_HSM>;
  119. clock-names = "pixel", "hdmi";
  120. dmas = <&dma 17>;
  121. dma-names = "audio-rx";
  122. status = "disabled";
  123. };
  124. v3d: v3d@7ec00000 {
  125. compatible = "brcm,bcm2835-v3d";
  126. reg = <0x7ec00000 0x1000>;
  127. interrupts = <1 10>;
  128. };
  129. vc4: gpu {
  130. compatible = "brcm,bcm2835-vc4";
  131. };
  132. };
  133. };
  134. &cpu_thermal {
  135. thermal-sensors = <&thermal>;
  136. };
  137. &gpio {
  138. i2c_slave_gpio18: i2c_slave_gpio18 {
  139. brcm,pins = <18 19 20 21>;
  140. brcm,function = <BCM2835_FSEL_ALT3>;
  141. };
  142. jtag_gpio4: jtag_gpio4 {
  143. brcm,pins = <4 5 6 12 13>;
  144. brcm,function = <BCM2835_FSEL_ALT5>;
  145. };
  146. pwm0_gpio12: pwm0_gpio12 {
  147. brcm,pins = <12>;
  148. brcm,function = <BCM2835_FSEL_ALT0>;
  149. };
  150. pwm0_gpio18: pwm0_gpio18 {
  151. brcm,pins = <18>;
  152. brcm,function = <BCM2835_FSEL_ALT5>;
  153. };
  154. pwm0_gpio40: pwm0_gpio40 {
  155. brcm,pins = <40>;
  156. brcm,function = <BCM2835_FSEL_ALT0>;
  157. };
  158. pwm1_gpio13: pwm1_gpio13 {
  159. brcm,pins = <13>;
  160. brcm,function = <BCM2835_FSEL_ALT0>;
  161. };
  162. pwm1_gpio19: pwm1_gpio19 {
  163. brcm,pins = <19>;
  164. brcm,function = <BCM2835_FSEL_ALT5>;
  165. };
  166. pwm1_gpio41: pwm1_gpio41 {
  167. brcm,pins = <41>;
  168. brcm,function = <BCM2835_FSEL_ALT0>;
  169. };
  170. pwm1_gpio45: pwm1_gpio45 {
  171. brcm,pins = <45>;
  172. brcm,function = <BCM2835_FSEL_ALT0>;
  173. };
  174. };
  175. &i2s {
  176. dmas = <&dma 2>, <&dma 3>;
  177. dma-names = "tx", "rx";
  178. };
  179. &sdhost {
  180. dmas = <&dma 13>;
  181. dma-names = "rx-tx";
  182. };
  183. &spi {
  184. dmas = <&dma 6>, <&dma 7>;
  185. dma-names = "tx", "rx";
  186. };