bcm23550.dtsi 10 KB

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  1. /*
  2. * BSD LICENSE
  3. *
  4. * Copyright(c) 2016 Broadcom. All rights reserved.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions
  8. * are met:
  9. *
  10. * * Redistributions of source code must retain the above copyright
  11. * notice, this list of conditions and the following disclaimer.
  12. * * Redistributions in binary form must reproduce the above copyright
  13. * notice, this list of conditions and the following disclaimer in
  14. * the documentation and/or other materials provided with the
  15. * distribution.
  16. * * Neither the name of Broadcom Corporation nor the names of its
  17. * contributors may be used to endorse or promote products derived
  18. * from this software without specific prior written permission.
  19. *
  20. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  23. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  24. * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25. * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26. * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27. * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28. * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31. */
  32. #include <dt-bindings/interrupt-controller/arm-gic.h>
  33. #include <dt-bindings/interrupt-controller/irq.h>
  34. /* BCM23550 and BCM21664 have almost identical clocks */
  35. #include "dt-bindings/clock/bcm21664.h"
  36. / {
  37. #address-cells = <1>;
  38. #size-cells = <1>;
  39. model = "BCM23550 SoC";
  40. compatible = "brcm,bcm23550";
  41. interrupt-parent = <&gic>;
  42. cpus {
  43. #address-cells = <1>;
  44. #size-cells = <0>;
  45. cpu0: cpu@0 {
  46. device_type = "cpu";
  47. compatible = "arm,cortex-a7";
  48. reg = <0>;
  49. clock-frequency = <1000000000>;
  50. };
  51. cpu1: cpu@1 {
  52. device_type = "cpu";
  53. compatible = "arm,cortex-a7";
  54. enable-method = "brcm,bcm23550";
  55. secondary-boot-reg = <0x35004178>;
  56. reg = <1>;
  57. clock-frequency = <1000000000>;
  58. };
  59. cpu2: cpu@2 {
  60. device_type = "cpu";
  61. compatible = "arm,cortex-a7";
  62. enable-method = "brcm,bcm23550";
  63. secondary-boot-reg = <0x35004178>;
  64. reg = <2>;
  65. clock-frequency = <1000000000>;
  66. };
  67. cpu3: cpu@3 {
  68. device_type = "cpu";
  69. compatible = "arm,cortex-a7";
  70. enable-method = "brcm,bcm23550";
  71. secondary-boot-reg = <0x35004178>;
  72. reg = <3>;
  73. clock-frequency = <1000000000>;
  74. };
  75. };
  76. /* Hub bus */
  77. hub@34000000 {
  78. compatible = "simple-bus";
  79. ranges = <0 0x34000000 0x102f83ac>;
  80. #address-cells = <1>;
  81. #size-cells = <1>;
  82. smc@4e000 {
  83. compatible = "brcm,bcm23550-smc", "brcm,kona-smc";
  84. reg = <0x0004e000 0x400>; /* 1 KiB in SRAM */
  85. };
  86. resetmgr: reset-controller@1001f00 {
  87. compatible = "brcm,bcm21664-resetmgr";
  88. reg = <0x01001f00 0x24>;
  89. };
  90. gpio: gpio@1003000 {
  91. compatible = "brcm,bcm23550-gpio", "brcm,kona-gpio";
  92. reg = <0x01003000 0x524>;
  93. interrupts =
  94. <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH
  95. GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH
  96. GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH
  97. GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
  98. #gpio-cells = <2>;
  99. #interrupt-cells = <2>;
  100. gpio-controller;
  101. interrupt-controller;
  102. };
  103. timer@1006000 {
  104. compatible = "brcm,kona-timer";
  105. reg = <0x01006000 0x1c>;
  106. interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
  107. clocks = <&aon_ccu BCM21664_AON_CCU_HUB_TIMER>;
  108. };
  109. };
  110. /* Slaves bus */
  111. slaves@3e000000 {
  112. compatible = "simple-bus";
  113. ranges = <0 0x3e000000 0x0001c070>;
  114. #address-cells = <1>;
  115. #size-cells = <1>;
  116. uartb: serial@0 {
  117. compatible = "snps,dw-apb-uart";
  118. status = "disabled";
  119. reg = <0x00000000 0x118>;
  120. clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB>;
  121. interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
  122. reg-shift = <2>;
  123. reg-io-width = <4>;
  124. };
  125. uartb2: serial@1000 {
  126. compatible = "snps,dw-apb-uart";
  127. status = "disabled";
  128. reg = <0x00001000 0x118>;
  129. clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB2>;
  130. interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
  131. reg-shift = <2>;
  132. reg-io-width = <4>;
  133. };
  134. uartb3: serial@2000 {
  135. compatible = "snps,dw-apb-uart";
  136. status = "disabled";
  137. reg = <0x00002000 0x118>;
  138. clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB3>;
  139. interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
  140. reg-shift = <2>;
  141. reg-io-width = <4>;
  142. };
  143. bsc1: i2c@16000 {
  144. compatible = "brcm,kona-i2c";
  145. reg = <0x00016000 0x70>;
  146. interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
  147. #address-cells = <1>;
  148. #size-cells = <0>;
  149. clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC1>;
  150. status = "disabled";
  151. };
  152. bsc2: i2c@17000 {
  153. compatible = "brcm,kona-i2c";
  154. reg = <0x00017000 0x70>;
  155. interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
  156. #address-cells = <1>;
  157. #size-cells = <0>;
  158. clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC2>;
  159. status = "disabled";
  160. };
  161. bsc3: i2c@18000 {
  162. compatible = "brcm,kona-i2c";
  163. reg = <0x00018000 0x70>;
  164. interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
  165. #address-cells = <1>;
  166. #size-cells = <0>;
  167. clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC3>;
  168. status = "disabled";
  169. };
  170. bsc4: i2c@1c000 {
  171. compatible = "brcm,kona-i2c";
  172. reg = <0x0001c000 0x70>;
  173. interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
  174. #address-cells = <1>;
  175. #size-cells = <0>;
  176. clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC4>;
  177. status = "disabled";
  178. };
  179. };
  180. /* Apps bus */
  181. apps@3e300000 {
  182. compatible = "simple-bus";
  183. ranges = <0 0x3e300000 0x01b77000>;
  184. #address-cells = <1>;
  185. #size-cells = <1>;
  186. usbotg: usb@e20000 {
  187. compatible = "snps,dwc2";
  188. reg = <0x00e20000 0x10000>;
  189. interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
  190. clocks = <&usb_otg_ahb_clk>;
  191. clock-names = "otg";
  192. phys = <&usbphy>;
  193. phy-names = "usb2-phy";
  194. status = "disabled";
  195. };
  196. usbphy: usb-phy@e30000 {
  197. compatible = "brcm,kona-usb2-phy";
  198. reg = <0x00e30000 0x28>;
  199. #phy-cells = <0>;
  200. status = "disabled";
  201. };
  202. sdio1: sdio@e80000 {
  203. compatible = "brcm,kona-sdhci";
  204. reg = <0x00e80000 0x801c>;
  205. interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
  206. clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO1>;
  207. status = "disabled";
  208. };
  209. sdio2: sdio@e90000 {
  210. compatible = "brcm,kona-sdhci";
  211. reg = <0x00e90000 0x801c>;
  212. interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
  213. clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO2>;
  214. status = "disabled";
  215. };
  216. sdio3: sdio@ea0000 {
  217. compatible = "brcm,kona-sdhci";
  218. reg = <0x00ea0000 0x801c>;
  219. interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
  220. clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO3>;
  221. status = "disabled";
  222. };
  223. sdio4: sdio@eb0000 {
  224. compatible = "brcm,kona-sdhci";
  225. reg = <0x00eb0000 0x801c>;
  226. interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  227. clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO4>;
  228. status = "disabled";
  229. };
  230. cdc: cdc@1b0e000 {
  231. compatible = "brcm,bcm23550-cdc";
  232. reg = <0x01b0e000 0x78>;
  233. };
  234. gic: interrupt-controller@1b21000 {
  235. compatible = "arm,cortex-a9-gic";
  236. #interrupt-cells = <3>;
  237. #address-cells = <0>;
  238. interrupt-controller;
  239. reg = <0x01b21000 0x1000>,
  240. <0x01b22000 0x1000>;
  241. };
  242. };
  243. clocks {
  244. #address-cells = <1>;
  245. #size-cells = <1>;
  246. ranges;
  247. /*
  248. * Fixed clocks are defined before CCUs whose
  249. * clocks may depend on them.
  250. */
  251. ref_32k_clk: ref_32k {
  252. #clock-cells = <0>;
  253. compatible = "fixed-clock";
  254. clock-frequency = <32768>;
  255. };
  256. bbl_32k_clk: bbl_32k {
  257. #clock-cells = <0>;
  258. compatible = "fixed-clock";
  259. clock-frequency = <32768>;
  260. };
  261. ref_13m_clk: ref_13m {
  262. #clock-cells = <0>;
  263. compatible = "fixed-clock";
  264. clock-frequency = <13000000>;
  265. };
  266. var_13m_clk: var_13m {
  267. #clock-cells = <0>;
  268. compatible = "fixed-clock";
  269. clock-frequency = <13000000>;
  270. };
  271. dft_19_5m_clk: dft_19_5m {
  272. #clock-cells = <0>;
  273. compatible = "fixed-clock";
  274. clock-frequency = <19500000>;
  275. };
  276. ref_crystal_clk: ref_crystal {
  277. #clock-cells = <0>;
  278. compatible = "fixed-clock";
  279. clock-frequency = <26000000>;
  280. };
  281. ref_52m_clk: ref_52m {
  282. #clock-cells = <0>;
  283. compatible = "fixed-clock";
  284. clock-frequency = <52000000>;
  285. };
  286. var_52m_clk: var_52m {
  287. #clock-cells = <0>;
  288. compatible = "fixed-clock";
  289. clock-frequency = <52000000>;
  290. };
  291. usb_otg_ahb_clk: usb_otg_ahb {
  292. #clock-cells = <0>;
  293. compatible = "fixed-clock";
  294. clock-frequency = <52000000>;
  295. };
  296. ref_96m_clk: ref_96m {
  297. #clock-cells = <0>;
  298. compatible = "fixed-clock";
  299. clock-frequency = <96000000>;
  300. };
  301. var_96m_clk: var_96m {
  302. #clock-cells = <0>;
  303. compatible = "fixed-clock";
  304. clock-frequency = <96000000>;
  305. };
  306. ref_104m_clk: ref_104m {
  307. #clock-cells = <0>;
  308. compatible = "fixed-clock";
  309. clock-frequency = <104000000>;
  310. };
  311. var_104m_clk: var_104m {
  312. #clock-cells = <0>;
  313. compatible = "fixed-clock";
  314. clock-frequency = <104000000>;
  315. };
  316. ref_156m_clk: ref_156m {
  317. #clock-cells = <0>;
  318. compatible = "fixed-clock";
  319. clock-frequency = <156000000>;
  320. };
  321. var_156m_clk: var_156m {
  322. #clock-cells = <0>;
  323. compatible = "fixed-clock";
  324. clock-frequency = <156000000>;
  325. };
  326. root_ccu: root_ccu@35001000 {
  327. compatible = BCM21664_DT_ROOT_CCU_COMPAT;
  328. reg = <0x35001000 0x0f00>;
  329. #clock-cells = <1>;
  330. clock-output-names = "frac_1m";
  331. };
  332. aon_ccu: aon_ccu@35002000 {
  333. compatible = BCM21664_DT_AON_CCU_COMPAT;
  334. reg = <0x35002000 0x0f00>;
  335. #clock-cells = <1>;
  336. clock-output-names = "hub_timer";
  337. };
  338. slave_ccu: slave_ccu@3e011000 {
  339. compatible = BCM21664_DT_SLAVE_CCU_COMPAT;
  340. reg = <0x3e011000 0x0f00>;
  341. #clock-cells = <1>;
  342. clock-output-names = "uartb",
  343. "uartb2",
  344. "uartb3",
  345. "bsc1",
  346. "bsc2",
  347. "bsc3",
  348. "bsc4";
  349. };
  350. master_ccu: master_ccu@3f001000 {
  351. compatible = BCM21664_DT_MASTER_CCU_COMPAT;
  352. reg = <0x3f001000 0x0f00>;
  353. #clock-cells = <1>;
  354. clock-output-names = "sdio1",
  355. "sdio2",
  356. "sdio3",
  357. "sdio4",
  358. "sdio1_sleep",
  359. "sdio2_sleep",
  360. "sdio3_sleep",
  361. "sdio4_sleep";
  362. };
  363. };
  364. };