bcm11351.dtsi 9.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. // Copyright (C) 2012-2013 Broadcom Corporation
  3. #include <dt-bindings/interrupt-controller/arm-gic.h>
  4. #include <dt-bindings/interrupt-controller/irq.h>
  5. #include "dt-bindings/clock/bcm281xx.h"
  6. / {
  7. #address-cells = <1>;
  8. #size-cells = <1>;
  9. model = "BCM11351 SoC";
  10. compatible = "brcm,bcm11351";
  11. interrupt-parent = <&gic>;
  12. chosen {
  13. bootargs = "console=ttyS0,115200n8";
  14. };
  15. cpus {
  16. #address-cells = <1>;
  17. #size-cells = <0>;
  18. cpu0: cpu@0 {
  19. device_type = "cpu";
  20. compatible = "arm,cortex-a9";
  21. reg = <0>;
  22. };
  23. cpu1: cpu@1 {
  24. device_type = "cpu";
  25. compatible = "arm,cortex-a9";
  26. enable-method = "brcm,bcm11351-cpu-method";
  27. secondary-boot-reg = <0x3500417c>;
  28. reg = <1>;
  29. };
  30. };
  31. gic: interrupt-controller@3ff00100 {
  32. compatible = "arm,cortex-a9-gic";
  33. #interrupt-cells = <3>;
  34. #address-cells = <0>;
  35. interrupt-controller;
  36. reg = <0x3ff01000 0x1000>,
  37. <0x3ff00100 0x100>;
  38. };
  39. smc@3404c000 {
  40. compatible = "brcm,bcm11351-smc", "brcm,kona-smc";
  41. reg = <0x3404c000 0x400>; /* 1 KiB in SRAM */
  42. };
  43. uart@3e000000 {
  44. compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
  45. status = "disabled";
  46. reg = <0x3e000000 0x1000>;
  47. clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB>;
  48. interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
  49. reg-shift = <2>;
  50. reg-io-width = <4>;
  51. };
  52. uart@3e001000 {
  53. compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
  54. status = "disabled";
  55. reg = <0x3e001000 0x1000>;
  56. clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB2>;
  57. interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
  58. reg-shift = <2>;
  59. reg-io-width = <4>;
  60. };
  61. uart@3e002000 {
  62. compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
  63. status = "disabled";
  64. reg = <0x3e002000 0x1000>;
  65. clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB3>;
  66. interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
  67. reg-shift = <2>;
  68. reg-io-width = <4>;
  69. };
  70. uart@3e003000 {
  71. compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
  72. status = "disabled";
  73. reg = <0x3e003000 0x1000>;
  74. clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB4>;
  75. interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
  76. reg-shift = <2>;
  77. reg-io-width = <4>;
  78. };
  79. L2: l2-cache@3ff20000 {
  80. compatible = "brcm,bcm11351-a2-pl310-cache";
  81. reg = <0x3ff20000 0x1000>;
  82. cache-unified;
  83. cache-level = <2>;
  84. };
  85. watchdog@35002f40 {
  86. compatible = "brcm,bcm11351-wdt", "brcm,kona-wdt";
  87. reg = <0x35002f40 0x6c>;
  88. };
  89. timer@35006000 {
  90. compatible = "brcm,kona-timer";
  91. reg = <0x35006000 0x1000>;
  92. interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
  93. clocks = <&aon_ccu BCM281XX_AON_CCU_HUB_TIMER>;
  94. };
  95. gpio: gpio@35003000 {
  96. compatible = "brcm,bcm11351-gpio", "brcm,kona-gpio";
  97. reg = <0x35003000 0x800>;
  98. interrupts =
  99. <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH
  100. GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH
  101. GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH
  102. GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
  103. GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
  104. GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
  105. #gpio-cells = <2>;
  106. #interrupt-cells = <2>;
  107. gpio-controller;
  108. interrupt-controller;
  109. };
  110. sdio1: sdio@3f180000 {
  111. compatible = "brcm,kona-sdhci";
  112. reg = <0x3f180000 0x10000>;
  113. interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
  114. clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO1>;
  115. status = "disabled";
  116. };
  117. sdio2: sdio@3f190000 {
  118. compatible = "brcm,kona-sdhci";
  119. reg = <0x3f190000 0x10000>;
  120. interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
  121. clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO2>;
  122. status = "disabled";
  123. };
  124. sdio3: sdio@3f1a0000 {
  125. compatible = "brcm,kona-sdhci";
  126. reg = <0x3f1a0000 0x10000>;
  127. interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
  128. clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO3>;
  129. status = "disabled";
  130. };
  131. sdio4: sdio@3f1b0000 {
  132. compatible = "brcm,kona-sdhci";
  133. reg = <0x3f1b0000 0x10000>;
  134. interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  135. clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO4>;
  136. status = "disabled";
  137. };
  138. pinctrl@35004800 {
  139. compatible = "brcm,bcm11351-pinctrl";
  140. reg = <0x35004800 0x430>;
  141. };
  142. i2c@3e016000 {
  143. compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c";
  144. reg = <0x3e016000 0x80>;
  145. interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
  146. #address-cells = <1>;
  147. #size-cells = <0>;
  148. clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC1>;
  149. status = "disabled";
  150. };
  151. i2c@3e017000 {
  152. compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c";
  153. reg = <0x3e017000 0x80>;
  154. interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
  155. #address-cells = <1>;
  156. #size-cells = <0>;
  157. clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC2>;
  158. status = "disabled";
  159. };
  160. i2c@3e018000 {
  161. compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c";
  162. reg = <0x3e018000 0x80>;
  163. interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
  164. #address-cells = <1>;
  165. #size-cells = <0>;
  166. clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC3>;
  167. status = "disabled";
  168. };
  169. i2c@3500d000 {
  170. compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c";
  171. reg = <0x3500d000 0x80>;
  172. interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
  173. #address-cells = <1>;
  174. #size-cells = <0>;
  175. clocks = <&aon_ccu BCM281XX_AON_CCU_PMU_BSC>;
  176. status = "disabled";
  177. };
  178. pwm: pwm@3e01a000 {
  179. compatible = "brcm,bcm11351-pwm", "brcm,kona-pwm";
  180. reg = <0x3e01a000 0xcc>;
  181. clocks = <&slave_ccu BCM281XX_SLAVE_CCU_PWM>;
  182. #pwm-cells = <3>;
  183. status = "disabled";
  184. };
  185. clocks {
  186. #address-cells = <1>;
  187. #size-cells = <1>;
  188. ranges;
  189. root_ccu: root_ccu@35001000 {
  190. compatible = "brcm,bcm11351-root-ccu";
  191. reg = <0x35001000 0x0f00>;
  192. #clock-cells = <1>;
  193. clock-output-names = "frac_1m";
  194. };
  195. hub_ccu: hub_ccu@34000000 {
  196. compatible = "brcm,bcm11351-hub-ccu";
  197. reg = <0x34000000 0x0f00>;
  198. #clock-cells = <1>;
  199. clock-output-names = "tmon_1m";
  200. };
  201. aon_ccu: aon_ccu@35002000 {
  202. compatible = "brcm,bcm11351-aon-ccu";
  203. reg = <0x35002000 0x0f00>;
  204. #clock-cells = <1>;
  205. clock-output-names = "hub_timer",
  206. "pmu_bsc",
  207. "pmu_bsc_var";
  208. };
  209. master_ccu: master_ccu@3f001000 {
  210. compatible = "brcm,bcm11351-master-ccu";
  211. reg = <0x3f001000 0x0f00>;
  212. #clock-cells = <1>;
  213. clock-output-names = "sdio1",
  214. "sdio2",
  215. "sdio3",
  216. "sdio4",
  217. "usb_ic",
  218. "hsic2_48m",
  219. "hsic2_12m";
  220. };
  221. slave_ccu: slave_ccu@3e011000 {
  222. compatible = "brcm,bcm11351-slave-ccu";
  223. reg = <0x3e011000 0x0f00>;
  224. #clock-cells = <1>;
  225. clock-output-names = "uartb",
  226. "uartb2",
  227. "uartb3",
  228. "uartb4",
  229. "ssp0",
  230. "ssp2",
  231. "bsc1",
  232. "bsc2",
  233. "bsc3",
  234. "pwm";
  235. };
  236. ref_1m_clk: ref_1m {
  237. #clock-cells = <0>;
  238. compatible = "fixed-clock";
  239. clock-frequency = <1000000>;
  240. };
  241. ref_32k_clk: ref_32k {
  242. #clock-cells = <0>;
  243. compatible = "fixed-clock";
  244. clock-frequency = <32768>;
  245. };
  246. bbl_32k_clk: bbl_32k {
  247. #clock-cells = <0>;
  248. compatible = "fixed-clock";
  249. clock-frequency = <32768>;
  250. };
  251. ref_13m_clk: ref_13m {
  252. #clock-cells = <0>;
  253. compatible = "fixed-clock";
  254. clock-frequency = <13000000>;
  255. };
  256. var_13m_clk: var_13m {
  257. #clock-cells = <0>;
  258. compatible = "fixed-clock";
  259. clock-frequency = <13000000>;
  260. };
  261. dft_19_5m_clk: dft_19_5m {
  262. #clock-cells = <0>;
  263. compatible = "fixed-clock";
  264. clock-frequency = <19500000>;
  265. };
  266. ref_crystal_clk: ref_crystal {
  267. #clock-cells = <0>;
  268. compatible = "fixed-clock";
  269. clock-frequency = <26000000>;
  270. };
  271. ref_cx40_clk: ref_cx40 {
  272. #clock-cells = <0>;
  273. compatible = "fixed-clock";
  274. clock-frequency = <40000000>;
  275. };
  276. ref_52m_clk: ref_52m {
  277. #clock-cells = <0>;
  278. compatible = "fixed-clock";
  279. clock-frequency = <52000000>;
  280. };
  281. var_52m_clk: var_52m {
  282. #clock-cells = <0>;
  283. compatible = "fixed-clock";
  284. clock-frequency = <52000000>;
  285. };
  286. usb_otg_ahb_clk: usb_otg_ahb {
  287. compatible = "fixed-clock";
  288. clock-frequency = <52000000>;
  289. #clock-cells = <0>;
  290. };
  291. ref_96m_clk: ref_96m {
  292. #clock-cells = <0>;
  293. compatible = "fixed-clock";
  294. clock-frequency = <96000000>;
  295. };
  296. var_96m_clk: var_96m {
  297. #clock-cells = <0>;
  298. compatible = "fixed-clock";
  299. clock-frequency = <96000000>;
  300. };
  301. ref_104m_clk: ref_104m {
  302. #clock-cells = <0>;
  303. compatible = "fixed-clock";
  304. clock-frequency = <104000000>;
  305. };
  306. var_104m_clk: var_104m {
  307. #clock-cells = <0>;
  308. compatible = "fixed-clock";
  309. clock-frequency = <104000000>;
  310. };
  311. ref_156m_clk: ref_156m {
  312. #clock-cells = <0>;
  313. compatible = "fixed-clock";
  314. clock-frequency = <156000000>;
  315. };
  316. var_156m_clk: var_156m {
  317. #clock-cells = <0>;
  318. compatible = "fixed-clock";
  319. clock-frequency = <156000000>;
  320. };
  321. ref_208m_clk: ref_208m {
  322. #clock-cells = <0>;
  323. compatible = "fixed-clock";
  324. clock-frequency = <208000000>;
  325. };
  326. var_208m_clk: var_208m {
  327. #clock-cells = <0>;
  328. compatible = "fixed-clock";
  329. clock-frequency = <208000000>;
  330. };
  331. ref_312m_clk: ref_312m {
  332. #clock-cells = <0>;
  333. compatible = "fixed-clock";
  334. clock-frequency = <312000000>;
  335. };
  336. var_312m_clk: var_312m {
  337. #clock-cells = <0>;
  338. compatible = "fixed-clock";
  339. clock-frequency = <312000000>;
  340. };
  341. };
  342. usbotg: usb@3f120000 {
  343. compatible = "snps,dwc2";
  344. reg = <0x3f120000 0x10000>;
  345. interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
  346. clocks = <&usb_otg_ahb_clk>;
  347. clock-names = "otg";
  348. phys = <&usbphy>;
  349. phy-names = "usb2-phy";
  350. status = "disabled";
  351. };
  352. usbphy: usb-phy@3f130000 {
  353. compatible = "brcm,kona-usb2-phy";
  354. reg = <0x3f130000 0x28>;
  355. #phy-cells = <0>;
  356. status = "disabled";
  357. };
  358. };