axm55xx.dtsi 4.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * arch/arm/boot/dts/axm55xx.dtsi
  4. *
  5. * Copyright (C) 2013 LSI
  6. */
  7. #include <dt-bindings/interrupt-controller/arm-gic.h>
  8. #include <dt-bindings/clock/lsi,axm5516-clks.h>
  9. / {
  10. #address-cells = <2>;
  11. #size-cells = <2>;
  12. interrupt-parent = <&gic>;
  13. aliases {
  14. serial0 = &serial0;
  15. serial1 = &serial1;
  16. serial2 = &serial2;
  17. serial3 = &serial3;
  18. timer = &timer0;
  19. };
  20. clocks {
  21. compatible = "simple-bus";
  22. #address-cells = <2>;
  23. #size-cells = <2>;
  24. ranges;
  25. clk_ref0: clk_ref0 {
  26. compatible = "fixed-clock";
  27. #clock-cells = <0>;
  28. clock-frequency = <125000000>;
  29. };
  30. clk_ref1: clk_ref1 {
  31. compatible = "fixed-clock";
  32. #clock-cells = <0>;
  33. clock-frequency = <125000000>;
  34. };
  35. clk_ref2: clk_ref2 {
  36. compatible = "fixed-clock";
  37. #clock-cells = <0>;
  38. clock-frequency = <125000000>;
  39. };
  40. clks: clock-controller@2010020000 {
  41. compatible = "lsi,axm5516-clks";
  42. #clock-cells = <1>;
  43. reg = <0x20 0x10020000 0 0x20000>;
  44. };
  45. };
  46. gic: interrupt-controller@2001001000 {
  47. compatible = "arm,cortex-a15-gic";
  48. #interrupt-cells = <3>;
  49. #address-cells = <0>;
  50. interrupt-controller;
  51. reg = <0x20 0x01001000 0 0x1000>,
  52. <0x20 0x01002000 0 0x2000>,
  53. <0x20 0x01004000 0 0x2000>,
  54. <0x20 0x01006000 0 0x2000>;
  55. interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
  56. IRQ_TYPE_LEVEL_HIGH)>;
  57. };
  58. timer {
  59. compatible = "arm,armv7-timer";
  60. interrupts =
  61. <GIC_PPI 13
  62. (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  63. <GIC_PPI 14
  64. (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  65. <GIC_PPI 11
  66. (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  67. <GIC_PPI 10
  68. (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  69. };
  70. pmu {
  71. compatible = "arm,cortex-a15-pmu";
  72. interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
  73. };
  74. soc {
  75. compatible = "simple-bus";
  76. device_type = "soc";
  77. #address-cells = <2>;
  78. #size-cells = <2>;
  79. interrupt-parent = <&gic>;
  80. ranges;
  81. syscon: syscon@2010030000 {
  82. compatible = "lsi,axxia-syscon", "syscon";
  83. reg = <0x20 0x10030000 0 0x2000>;
  84. };
  85. reset: reset@2010031000 {
  86. compatible = "lsi,axm55xx-reset";
  87. syscon = <&syscon>;
  88. };
  89. amba {
  90. compatible = "simple-bus";
  91. #address-cells = <2>;
  92. #size-cells = <2>;
  93. ranges;
  94. serial0: uart@2010080000 {
  95. compatible = "arm,pl011", "arm,primecell";
  96. reg = <0x20 0x10080000 0 0x1000>;
  97. interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
  98. clocks = <&clks AXXIA_CLK_PER>;
  99. clock-names = "apb_pclk";
  100. status = "disabled";
  101. };
  102. serial1: uart@2010081000 {
  103. compatible = "arm,pl011", "arm,primecell";
  104. reg = <0x20 0x10081000 0 0x1000>;
  105. interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
  106. clocks = <&clks AXXIA_CLK_PER>;
  107. clock-names = "apb_pclk";
  108. status = "disabled";
  109. };
  110. serial2: uart@2010082000 {
  111. compatible = "arm,pl011", "arm,primecell";
  112. reg = <0x20 0x10082000 0 0x1000>;
  113. interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
  114. clocks = <&clks AXXIA_CLK_PER>;
  115. clock-names = "apb_pclk";
  116. status = "disabled";
  117. };
  118. serial3: uart@2010083000 {
  119. compatible = "arm,pl011", "arm,primecell";
  120. reg = <0x20 0x10083000 0 0x1000>;
  121. interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
  122. clocks = <&clks AXXIA_CLK_PER>;
  123. clock-names = "apb_pclk";
  124. status = "disabled";
  125. };
  126. timer0: timer@2010091000 {
  127. compatible = "arm,sp804", "arm,primecell";
  128. reg = <0x20 0x10091000 0 0x1000>;
  129. interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
  130. <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
  131. <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
  132. <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
  133. <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
  134. <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
  135. <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
  136. <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
  137. <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
  138. clocks = <&clks AXXIA_CLK_PER>;
  139. clock-names = "apb_pclk";
  140. status = "okay";
  141. };
  142. gpio0: gpio@2010092000 {
  143. #gpio-cells = <2>;
  144. compatible = "arm,pl061", "arm,primecell";
  145. gpio-controller;
  146. reg = <0x20 0x10092000 0x00 0x1000>;
  147. interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
  148. <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
  149. <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
  150. <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
  151. <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
  152. <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
  153. <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
  154. <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
  155. clocks = <&clks AXXIA_CLK_PER>;
  156. clock-names = "apb_pclk";
  157. status = "disabled";
  158. };
  159. gpio1: gpio@2010093000 {
  160. #gpio-cells = <2>;
  161. compatible = "arm,pl061", "arm,primecell";
  162. gpio-controller;
  163. reg = <0x20 0x10093000 0x00 0x1000>;
  164. interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
  165. clocks = <&clks AXXIA_CLK_PER>;
  166. clock-names = "apb_pclk";
  167. status = "disabled";
  168. };
  169. };
  170. };
  171. };
  172. /*
  173. Local Variables:
  174. mode: C
  175. End:
  176. */