at91-sama5d27_som1.dtsi 3.5 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * at91-sama5d27_som1.dtsi - Device Tree file for SAMA5D27 SoM1 board
  4. *
  5. * Copyright (c) 2017, Microchip Technology Inc.
  6. * 2017 Cristian Birsan <[email protected]>
  7. * 2017 Claudiu Beznea <[email protected]>
  8. */
  9. #include "sama5d2.dtsi"
  10. #include "sama5d2-pinfunc.h"
  11. #include <dt-bindings/gpio/gpio.h>
  12. / {
  13. model = "Atmel SAMA5D27 SoM1";
  14. compatible = "atmel,sama5d27-som1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5";
  15. aliases {
  16. i2c0 = &i2c0;
  17. };
  18. clocks {
  19. slow_xtal {
  20. clock-frequency = <32768>;
  21. };
  22. main_xtal {
  23. clock-frequency = <24000000>;
  24. };
  25. };
  26. ahb {
  27. sdmmc0: sdio-host@a0000000 {
  28. microchip,sdcal-inverted;
  29. };
  30. apb {
  31. qspi1: spi@f0024000 {
  32. pinctrl-names = "default";
  33. pinctrl-0 = <&pinctrl_qspi1_default>;
  34. flash@0 {
  35. #address-cells = <1>;
  36. #size-cells = <1>;
  37. compatible = "jedec,spi-nor";
  38. reg = <0>;
  39. spi-max-frequency = <80000000>;
  40. spi-tx-bus-width = <4>;
  41. spi-rx-bus-width = <4>;
  42. m25p,fast-read;
  43. at91bootstrap@0 {
  44. label = "at91bootstrap";
  45. reg = <0x00000000 0x00040000>;
  46. };
  47. bootloader@40000 {
  48. label = "bootloader";
  49. reg = <0x00040000 0x000c0000>;
  50. };
  51. bootloaderenvred@100000 {
  52. label = "bootloader env redundant";
  53. reg = <0x00100000 0x00040000>;
  54. };
  55. bootloaderenv@140000 {
  56. label = "bootloader env";
  57. reg = <0x00140000 0x00040000>;
  58. };
  59. dtb@180000 {
  60. label = "device tree";
  61. reg = <0x00180000 0x00080000>;
  62. };
  63. kernel@200000 {
  64. label = "kernel";
  65. reg = <0x00200000 0x00600000>;
  66. };
  67. };
  68. };
  69. macb0: ethernet@f8008000 {
  70. pinctrl-names = "default";
  71. pinctrl-0 = <&pinctrl_macb0_default>;
  72. #address-cells = <1>;
  73. #size-cells = <0>;
  74. phy-mode = "rmii";
  75. ethernet-phy@7 {
  76. reg = <0x7>;
  77. interrupt-parent = <&pioA>;
  78. interrupts = <PIN_PD31 IRQ_TYPE_LEVEL_LOW>;
  79. pinctrl-names = "default";
  80. pinctrl-0 = <&pinctrl_macb0_phy_irq>;
  81. };
  82. };
  83. i2c0: i2c@f8028000 {
  84. dmas = <0>, <0>;
  85. pinctrl-names = "default", "gpio";
  86. pinctrl-0 = <&pinctrl_i2c0_default>;
  87. pinctrl-1 = <&pinctrl_i2c0_gpio>;
  88. sda-gpios = <&pioA PIN_PD21 GPIO_ACTIVE_HIGH>;
  89. scl-gpios = <&pioA PIN_PD22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  90. status = "okay";
  91. at24@50 {
  92. compatible = "atmel,24c02";
  93. reg = <0x50>;
  94. pagesize = <8>;
  95. };
  96. };
  97. pinctrl@fc038000 {
  98. pinctrl_i2c0_default: i2c0_default {
  99. pinmux = <PIN_PD21__TWD0>,
  100. <PIN_PD22__TWCK0>;
  101. bias-disable;
  102. };
  103. pinctrl_i2c0_gpio: i2c0_gpio {
  104. pinmux = <PIN_PD21__GPIO>,
  105. <PIN_PD22__GPIO>;
  106. bias-disable;
  107. };
  108. pinctrl_qspi1_default: qspi1_default {
  109. sck_cs {
  110. pinmux = <PIN_PB5__QSPI1_SCK>,
  111. <PIN_PB6__QSPI1_CS>;
  112. bias-disable;
  113. };
  114. data {
  115. pinmux = <PIN_PB7__QSPI1_IO0>,
  116. <PIN_PB8__QSPI1_IO1>,
  117. <PIN_PB9__QSPI1_IO2>,
  118. <PIN_PB10__QSPI1_IO3>;
  119. bias-pull-up;
  120. };
  121. };
  122. pinctrl_macb0_default: macb0_default {
  123. pinmux = <PIN_PD9__GTXCK>,
  124. <PIN_PD10__GTXEN>,
  125. <PIN_PD11__GRXDV>,
  126. <PIN_PD12__GRXER>,
  127. <PIN_PD13__GRX0>,
  128. <PIN_PD14__GRX1>,
  129. <PIN_PD15__GTX0>,
  130. <PIN_PD16__GTX1>,
  131. <PIN_PD17__GMDC>,
  132. <PIN_PD18__GMDIO>;
  133. bias-disable;
  134. };
  135. pinctrl_macb0_phy_irq: macb0_phy_irq {
  136. pinmux = <PIN_PD31__GPIO>;
  137. bias-disable;
  138. };
  139. };
  140. };
  141. };
  142. };