at91-q5xr5.dts 3.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Device Tree file for Exegin Q5xR5 board
  4. *
  5. * Copyright (C) 2014 Owen Kirby <[email protected]>
  6. */
  7. /dts-v1/;
  8. #include "at91sam9g20.dtsi"
  9. / {
  10. model = "Exegin Q5x (rev5)";
  11. compatible = "exegin,q5xr5", "atmel,at91sam9g20", "atmel,at91sam9";
  12. chosen {
  13. bootargs = "console=ttyS0,115200 rootfstype=squashfs,jffs2";
  14. };
  15. memory {
  16. reg = <0x20000000 0x0>;
  17. };
  18. clocks {
  19. #address-cells = <1>;
  20. #size-cells = <1>;
  21. ranges;
  22. main_clock: clock@0 {
  23. compatible = "atmel,osc", "fixed-clock";
  24. clock-frequency = <18432000>;
  25. };
  26. slow_xtal {
  27. clock-frequency = <32768>;
  28. };
  29. main_xtal {
  30. clock-frequency = <18432000>;
  31. };
  32. };
  33. };
  34. &dbgu {
  35. status = "okay";
  36. };
  37. &ebi {
  38. status = "okay";
  39. flash: flash@0 {
  40. compatible = "cfi-flash";
  41. #address-cells = <1>;
  42. #size-cells = <1>;
  43. reg = <0x0 0x1000000 0x800000>;
  44. bank-width = <2>;
  45. partitions {
  46. compatible = "fixed-partitions";
  47. #address-cells = <1>;
  48. #size-cells = <1>;
  49. kernel@0 {
  50. label = "kernel";
  51. reg = <0x0 0x200000>;
  52. };
  53. rootfs@200000 {
  54. label = "rootfs";
  55. reg = <0x200000 0x600000>;
  56. };
  57. };
  58. };
  59. };
  60. &macb0 {
  61. phy-mode = "mii";
  62. status = "okay";
  63. };
  64. &pinctrl {
  65. board {
  66. pinctrl_pck0_as_mck: pck0_as_mck {
  67. atmel,pins = <AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  68. };
  69. };
  70. spi0 {
  71. pinctrl_spi0: spi0-0 {
  72. atmel,pins =
  73. <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE
  74. AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE
  75. AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  76. };
  77. pinctrl_spi0_npcs0: spi0_npcs0 {
  78. atmel,pins = <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  79. };
  80. pinctrl_spi0_npcs1: spi0_npcs1 {
  81. atmel,pins = <AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  82. };
  83. };
  84. spi1 {
  85. pinctrl_spi1: spi1-0 {
  86. atmel,pins =
  87. <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE
  88. AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE
  89. AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  90. };
  91. pinctrl_spi1_npcs0: spi1_npcs0 {
  92. atmel,pins = <AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  93. };
  94. pinctrl_spi1_npcs1: spi1_npcs1 {
  95. atmel,pins = <AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  96. };
  97. };
  98. };
  99. &spi0 {
  100. pinctrl-names = "default";
  101. pinctrl-0 = <&pinctrl_spi0 &pinctrl_spi0_npcs0 &pinctrl_spi0_npcs1>;
  102. cs-gpios = <&pioA 3 GPIO_ACTIVE_HIGH>, <&pioC 11 GPIO_ACTIVE_LOW>, <0>, <0>;
  103. status = "okay";
  104. flash@0 {
  105. compatible = "jedec,spi-nor";
  106. spi-max-frequency = <20000000>;
  107. reg = <0>;
  108. #address-cells = <1>;
  109. #size-cells = <1>;
  110. at91boot@0 {
  111. label = "at91boot";
  112. reg = <0x0 0x4000>;
  113. };
  114. uenv@4000 {
  115. label = "uboot-env";
  116. reg = <0x4000 0x4000>;
  117. };
  118. uboot@8000 {
  119. label = "uboot";
  120. reg = <0x8000 0x3E000>;
  121. };
  122. };
  123. };
  124. &spi1 {
  125. pinctrl-names = "default";
  126. pinctrl-0 = <&pinctrl_spi1 &pinctrl_spi1_npcs0 &pinctrl_spi1_npcs1>;
  127. cs-gpios = <&pioB 3 GPIO_ACTIVE_HIGH>, <&pioC 5 GPIO_ACTIVE_LOW>, <0>, <0>;
  128. status = "okay";
  129. };
  130. &usart0 {
  131. pinctrl-0 =
  132. <&pinctrl_usart0
  133. &pinctrl_usart0_rts
  134. &pinctrl_usart0_cts
  135. &pinctrl_usart0_dtr_dsr
  136. &pinctrl_usart0_dcd
  137. &pinctrl_usart0_ri>;
  138. status = "okay";
  139. };
  140. &usb0 {
  141. num-ports = <2>;
  142. status = "okay";
  143. };
  144. &usb1 {
  145. status = "okay";
  146. };
  147. &watchdog {
  148. status = "okay";
  149. };