aspeed-g6.dtsi 29 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. // Copyright 2019 IBM Corp.
  3. #include <dt-bindings/interrupt-controller/arm-gic.h>
  4. #include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
  5. #include <dt-bindings/clock/ast2600-clock.h>
  6. / {
  7. model = "Aspeed BMC";
  8. compatible = "aspeed,ast2600";
  9. #address-cells = <1>;
  10. #size-cells = <1>;
  11. interrupt-parent = <&gic>;
  12. aliases {
  13. i2c0 = &i2c0;
  14. i2c1 = &i2c1;
  15. i2c2 = &i2c2;
  16. i2c3 = &i2c3;
  17. i2c4 = &i2c4;
  18. i2c5 = &i2c5;
  19. i2c6 = &i2c6;
  20. i2c7 = &i2c7;
  21. i2c8 = &i2c8;
  22. i2c9 = &i2c9;
  23. i2c10 = &i2c10;
  24. i2c11 = &i2c11;
  25. i2c12 = &i2c12;
  26. i2c13 = &i2c13;
  27. i2c14 = &i2c14;
  28. i2c15 = &i2c15;
  29. serial0 = &uart1;
  30. serial1 = &uart2;
  31. serial2 = &uart3;
  32. serial3 = &uart4;
  33. serial4 = &uart5;
  34. serial5 = &vuart1;
  35. serial6 = &vuart2;
  36. };
  37. cpus {
  38. #address-cells = <1>;
  39. #size-cells = <0>;
  40. enable-method = "aspeed,ast2600-smp";
  41. cpu@f00 {
  42. compatible = "arm,cortex-a7";
  43. device_type = "cpu";
  44. reg = <0xf00>;
  45. };
  46. cpu@f01 {
  47. compatible = "arm,cortex-a7";
  48. device_type = "cpu";
  49. reg = <0xf01>;
  50. };
  51. };
  52. timer {
  53. compatible = "arm,armv7-timer";
  54. interrupt-parent = <&gic>;
  55. interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  56. <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  57. <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  58. <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
  59. clocks = <&syscon ASPEED_CLK_HPLL>;
  60. arm,cpu-registers-not-fw-configured;
  61. always-on;
  62. };
  63. edac: sdram@1e6e0000 {
  64. compatible = "aspeed,ast2600-sdram-edac", "syscon";
  65. reg = <0x1e6e0000 0x174>;
  66. interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
  67. };
  68. ahb {
  69. compatible = "simple-bus";
  70. #address-cells = <1>;
  71. #size-cells = <1>;
  72. device_type = "soc";
  73. ranges;
  74. gic: interrupt-controller@40461000 {
  75. compatible = "arm,cortex-a7-gic";
  76. interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  77. #interrupt-cells = <3>;
  78. interrupt-controller;
  79. interrupt-parent = <&gic>;
  80. reg = <0x40461000 0x1000>,
  81. <0x40462000 0x1000>,
  82. <0x40464000 0x2000>,
  83. <0x40466000 0x2000>;
  84. };
  85. fmc: spi@1e620000 {
  86. reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
  87. #address-cells = <1>;
  88. #size-cells = <0>;
  89. compatible = "aspeed,ast2600-fmc";
  90. clocks = <&syscon ASPEED_CLK_AHB>;
  91. status = "disabled";
  92. interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
  93. flash@0 {
  94. reg = < 0 >;
  95. compatible = "jedec,spi-nor";
  96. spi-max-frequency = <50000000>;
  97. spi-rx-bus-width = <2>;
  98. status = "disabled";
  99. };
  100. flash@1 {
  101. reg = < 1 >;
  102. compatible = "jedec,spi-nor";
  103. spi-max-frequency = <50000000>;
  104. spi-rx-bus-width = <2>;
  105. status = "disabled";
  106. };
  107. flash@2 {
  108. reg = < 2 >;
  109. compatible = "jedec,spi-nor";
  110. spi-max-frequency = <50000000>;
  111. spi-rx-bus-width = <2>;
  112. status = "disabled";
  113. };
  114. };
  115. spi1: spi@1e630000 {
  116. reg = <0x1e630000 0xc4>, <0x30000000 0x10000000>;
  117. #address-cells = <1>;
  118. #size-cells = <0>;
  119. compatible = "aspeed,ast2600-spi";
  120. clocks = <&syscon ASPEED_CLK_AHB>;
  121. status = "disabled";
  122. flash@0 {
  123. reg = < 0 >;
  124. compatible = "jedec,spi-nor";
  125. spi-max-frequency = <50000000>;
  126. spi-rx-bus-width = <2>;
  127. status = "disabled";
  128. };
  129. flash@1 {
  130. reg = < 1 >;
  131. compatible = "jedec,spi-nor";
  132. spi-max-frequency = <50000000>;
  133. spi-rx-bus-width = <2>;
  134. status = "disabled";
  135. };
  136. };
  137. spi2: spi@1e631000 {
  138. reg = <0x1e631000 0xc4>, <0x50000000 0x10000000>;
  139. #address-cells = <1>;
  140. #size-cells = <0>;
  141. compatible = "aspeed,ast2600-spi";
  142. clocks = <&syscon ASPEED_CLK_AHB>;
  143. status = "disabled";
  144. flash@0 {
  145. reg = < 0 >;
  146. compatible = "jedec,spi-nor";
  147. spi-max-frequency = <50000000>;
  148. spi-rx-bus-width = <2>;
  149. status = "disabled";
  150. };
  151. flash@1 {
  152. reg = < 1 >;
  153. compatible = "jedec,spi-nor";
  154. spi-max-frequency = <50000000>;
  155. spi-rx-bus-width = <2>;
  156. status = "disabled";
  157. };
  158. flash@2 {
  159. reg = < 2 >;
  160. compatible = "jedec,spi-nor";
  161. spi-max-frequency = <50000000>;
  162. spi-rx-bus-width = <2>;
  163. status = "disabled";
  164. };
  165. };
  166. mdio0: mdio@1e650000 {
  167. compatible = "aspeed,ast2600-mdio";
  168. reg = <0x1e650000 0x8>;
  169. #address-cells = <1>;
  170. #size-cells = <0>;
  171. status = "disabled";
  172. pinctrl-names = "default";
  173. pinctrl-0 = <&pinctrl_mdio1_default>;
  174. resets = <&syscon ASPEED_RESET_MII>;
  175. };
  176. mdio1: mdio@1e650008 {
  177. compatible = "aspeed,ast2600-mdio";
  178. reg = <0x1e650008 0x8>;
  179. #address-cells = <1>;
  180. #size-cells = <0>;
  181. status = "disabled";
  182. pinctrl-names = "default";
  183. pinctrl-0 = <&pinctrl_mdio2_default>;
  184. resets = <&syscon ASPEED_RESET_MII>;
  185. };
  186. mdio2: mdio@1e650010 {
  187. compatible = "aspeed,ast2600-mdio";
  188. reg = <0x1e650010 0x8>;
  189. #address-cells = <1>;
  190. #size-cells = <0>;
  191. status = "disabled";
  192. pinctrl-names = "default";
  193. pinctrl-0 = <&pinctrl_mdio3_default>;
  194. resets = <&syscon ASPEED_RESET_MII>;
  195. };
  196. mdio3: mdio@1e650018 {
  197. compatible = "aspeed,ast2600-mdio";
  198. reg = <0x1e650018 0x8>;
  199. #address-cells = <1>;
  200. #size-cells = <0>;
  201. status = "disabled";
  202. pinctrl-names = "default";
  203. pinctrl-0 = <&pinctrl_mdio4_default>;
  204. resets = <&syscon ASPEED_RESET_MII>;
  205. };
  206. mac0: ftgmac@1e660000 {
  207. compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
  208. reg = <0x1e660000 0x180>;
  209. #address-cells = <1>;
  210. #size-cells = <0>;
  211. interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
  212. clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
  213. status = "disabled";
  214. };
  215. mac1: ftgmac@1e680000 {
  216. compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
  217. reg = <0x1e680000 0x180>;
  218. #address-cells = <1>;
  219. #size-cells = <0>;
  220. interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
  221. clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
  222. status = "disabled";
  223. };
  224. mac2: ftgmac@1e670000 {
  225. compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
  226. reg = <0x1e670000 0x180>;
  227. #address-cells = <1>;
  228. #size-cells = <0>;
  229. interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
  230. clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>;
  231. status = "disabled";
  232. };
  233. mac3: ftgmac@1e690000 {
  234. compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
  235. reg = <0x1e690000 0x180>;
  236. #address-cells = <1>;
  237. #size-cells = <0>;
  238. interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
  239. clocks = <&syscon ASPEED_CLK_GATE_MAC4CLK>;
  240. status = "disabled";
  241. };
  242. ehci0: usb@1e6a1000 {
  243. compatible = "aspeed,ast2600-ehci", "generic-ehci";
  244. reg = <0x1e6a1000 0x100>;
  245. interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
  246. clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
  247. pinctrl-names = "default";
  248. pinctrl-0 = <&pinctrl_usb2ah_default>;
  249. status = "disabled";
  250. };
  251. ehci1: usb@1e6a3000 {
  252. compatible = "aspeed,ast2600-ehci", "generic-ehci";
  253. reg = <0x1e6a3000 0x100>;
  254. interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
  255. clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>;
  256. pinctrl-names = "default";
  257. pinctrl-0 = <&pinctrl_usb2bh_default>;
  258. status = "disabled";
  259. };
  260. uhci: usb@1e6b0000 {
  261. compatible = "aspeed,ast2600-uhci", "generic-uhci";
  262. reg = <0x1e6b0000 0x100>;
  263. interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
  264. #ports = <2>;
  265. clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>;
  266. status = "disabled";
  267. /*
  268. * No default pinmux, it will follow EHCI, use an
  269. * explicit pinmux override if EHCI is not enabled.
  270. */
  271. };
  272. vhub: usb-vhub@1e6a0000 {
  273. compatible = "aspeed,ast2600-usb-vhub";
  274. reg = <0x1e6a0000 0x350>;
  275. interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
  276. clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
  277. aspeed,vhub-downstream-ports = <7>;
  278. aspeed,vhub-generic-endpoints = <21>;
  279. pinctrl-names = "default";
  280. pinctrl-0 = <&pinctrl_usb2ad_default>;
  281. status = "disabled";
  282. };
  283. udc: usb@1e6a2000 {
  284. compatible = "aspeed,ast2600-udc";
  285. reg = <0x1e6a2000 0x300>;
  286. interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
  287. clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>;
  288. pinctrl-names = "default";
  289. pinctrl-0 = <&pinctrl_usb2bd_default>;
  290. status = "disabled";
  291. };
  292. apb {
  293. compatible = "simple-bus";
  294. #address-cells = <1>;
  295. #size-cells = <1>;
  296. ranges;
  297. hace: crypto@1e6d0000 {
  298. compatible = "aspeed,ast2600-hace";
  299. reg = <0x1e6d0000 0x200>;
  300. interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
  301. clocks = <&syscon ASPEED_CLK_GATE_YCLK>;
  302. resets = <&syscon ASPEED_RESET_HACE>;
  303. };
  304. syscon: syscon@1e6e2000 {
  305. compatible = "aspeed,ast2600-scu", "syscon", "simple-mfd";
  306. reg = <0x1e6e2000 0x1000>;
  307. ranges = <0 0x1e6e2000 0x1000>;
  308. #address-cells = <1>;
  309. #size-cells = <1>;
  310. #clock-cells = <1>;
  311. #reset-cells = <1>;
  312. pinctrl: pinctrl {
  313. compatible = "aspeed,ast2600-pinctrl";
  314. };
  315. silicon-id@14 {
  316. compatible = "aspeed,ast2600-silicon-id", "aspeed,silicon-id";
  317. reg = <0x14 0x4 0x5b0 0x8>;
  318. };
  319. smp-memram@180 {
  320. compatible = "aspeed,ast2600-smpmem";
  321. reg = <0x180 0x40>;
  322. };
  323. scu_ic0: interrupt-controller@560 {
  324. #interrupt-cells = <1>;
  325. compatible = "aspeed,ast2600-scu-ic0";
  326. reg = <0x560 0x4>;
  327. interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
  328. interrupt-controller;
  329. };
  330. scu_ic1: interrupt-controller@570 {
  331. #interrupt-cells = <1>;
  332. compatible = "aspeed,ast2600-scu-ic1";
  333. reg = <0x570 0x4>;
  334. interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
  335. interrupt-controller;
  336. };
  337. };
  338. rng: hwrng@1e6e2524 {
  339. compatible = "timeriomem_rng";
  340. reg = <0x1e6e2524 0x4>;
  341. period = <1>;
  342. quality = <100>;
  343. };
  344. gfx: display@1e6e6000 {
  345. compatible = "aspeed,ast2600-gfx", "syscon";
  346. reg = <0x1e6e6000 0x1000>;
  347. reg-io-width = <4>;
  348. clocks = <&syscon ASPEED_CLK_GATE_D1CLK>;
  349. resets = <&syscon ASPEED_RESET_GRAPHICS>;
  350. syscon = <&syscon>;
  351. status = "disabled";
  352. interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
  353. };
  354. xdma: xdma@1e6e7000 {
  355. compatible = "aspeed,ast2600-xdma";
  356. reg = <0x1e6e7000 0x100>;
  357. clocks = <&syscon ASPEED_CLK_GATE_BCLK>;
  358. resets = <&syscon ASPEED_RESET_DEV_XDMA>, <&syscon ASPEED_RESET_RC_XDMA>;
  359. reset-names = "device", "root-complex";
  360. interrupts-extended = <&gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
  361. <&scu_ic0 ASPEED_AST2600_SCU_IC0_PCIE_PERST_LO_TO_HI>;
  362. aspeed,pcie-device = "bmc";
  363. aspeed,scu = <&syscon>;
  364. status = "disabled";
  365. };
  366. adc0: adc@1e6e9000 {
  367. compatible = "aspeed,ast2600-adc0";
  368. reg = <0x1e6e9000 0x100>;
  369. clocks = <&syscon ASPEED_CLK_APB2>;
  370. resets = <&syscon ASPEED_RESET_ADC>;
  371. interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
  372. #io-channel-cells = <1>;
  373. status = "disabled";
  374. };
  375. adc1: adc@1e6e9100 {
  376. compatible = "aspeed,ast2600-adc1";
  377. reg = <0x1e6e9100 0x100>;
  378. clocks = <&syscon ASPEED_CLK_APB2>;
  379. resets = <&syscon ASPEED_RESET_ADC>;
  380. interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
  381. #io-channel-cells = <1>;
  382. status = "disabled";
  383. };
  384. sbc: secure-boot-controller@1e6f2000 {
  385. compatible = "aspeed,ast2600-sbc";
  386. reg = <0x1e6f2000 0x1000>;
  387. };
  388. video: video@1e700000 {
  389. compatible = "aspeed,ast2600-video-engine";
  390. reg = <0x1e700000 0x1000>;
  391. clocks = <&syscon ASPEED_CLK_GATE_VCLK>,
  392. <&syscon ASPEED_CLK_GATE_ECLK>;
  393. clock-names = "vclk", "eclk";
  394. interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
  395. status = "disabled";
  396. };
  397. gpio0: gpio@1e780000 {
  398. #gpio-cells = <2>;
  399. gpio-controller;
  400. compatible = "aspeed,ast2600-gpio";
  401. reg = <0x1e780000 0x400>;
  402. interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
  403. gpio-ranges = <&pinctrl 0 0 208>;
  404. ngpios = <208>;
  405. clocks = <&syscon ASPEED_CLK_APB2>;
  406. interrupt-controller;
  407. #interrupt-cells = <2>;
  408. };
  409. sgpiom0: sgpiom@1e780500 {
  410. #gpio-cells = <2>;
  411. gpio-controller;
  412. compatible = "aspeed,ast2600-sgpiom";
  413. reg = <0x1e780500 0x100>;
  414. interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
  415. clocks = <&syscon ASPEED_CLK_APB2>;
  416. interrupt-controller;
  417. bus-frequency = <12000000>;
  418. pinctrl-names = "default";
  419. pinctrl-0 = <&pinctrl_sgpm1_default>;
  420. status = "disabled";
  421. };
  422. sgpiom1: sgpiom@1e780600 {
  423. #gpio-cells = <2>;
  424. gpio-controller;
  425. compatible = "aspeed,ast2600-sgpiom";
  426. reg = <0x1e780600 0x100>;
  427. interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
  428. clocks = <&syscon ASPEED_CLK_APB2>;
  429. interrupt-controller;
  430. bus-frequency = <12000000>;
  431. pinctrl-names = "default";
  432. pinctrl-0 = <&pinctrl_sgpm2_default>;
  433. status = "disabled";
  434. };
  435. gpio1: gpio@1e780800 {
  436. #gpio-cells = <2>;
  437. gpio-controller;
  438. compatible = "aspeed,ast2600-gpio";
  439. reg = <0x1e780800 0x800>;
  440. interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
  441. gpio-ranges = <&pinctrl 0 208 36>;
  442. ngpios = <36>;
  443. clocks = <&syscon ASPEED_CLK_APB1>;
  444. interrupt-controller;
  445. #interrupt-cells = <2>;
  446. };
  447. rtc: rtc@1e781000 {
  448. compatible = "aspeed,ast2600-rtc";
  449. reg = <0x1e781000 0x18>;
  450. interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
  451. status = "disabled";
  452. };
  453. timer: timer@1e782000 {
  454. compatible = "aspeed,ast2600-timer";
  455. reg = <0x1e782000 0x90>;
  456. interrupts-extended = <&gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
  457. <&gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
  458. <&gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
  459. <&gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
  460. <&gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
  461. <&gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
  462. <&gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
  463. <&gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
  464. clocks = <&syscon ASPEED_CLK_APB1>;
  465. clock-names = "PCLK";
  466. status = "disabled";
  467. };
  468. uart1: serial@1e783000 {
  469. compatible = "ns16550a";
  470. reg = <0x1e783000 0x20>;
  471. reg-shift = <2>;
  472. reg-io-width = <4>;
  473. interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
  474. clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
  475. resets = <&lpc_reset 4>;
  476. no-loopback-test;
  477. pinctrl-names = "default";
  478. pinctrl-0 = <&pinctrl_txd1_default &pinctrl_rxd1_default>;
  479. status = "disabled";
  480. };
  481. uart5: serial@1e784000 {
  482. compatible = "ns16550a";
  483. reg = <0x1e784000 0x1000>;
  484. reg-shift = <2>;
  485. interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
  486. clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
  487. no-loopback-test;
  488. };
  489. wdt1: watchdog@1e785000 {
  490. compatible = "aspeed,ast2600-wdt";
  491. reg = <0x1e785000 0x40>;
  492. };
  493. wdt2: watchdog@1e785040 {
  494. compatible = "aspeed,ast2600-wdt";
  495. reg = <0x1e785040 0x40>;
  496. status = "disabled";
  497. };
  498. wdt3: watchdog@1e785080 {
  499. compatible = "aspeed,ast2600-wdt";
  500. reg = <0x1e785080 0x40>;
  501. status = "disabled";
  502. };
  503. wdt4: watchdog@1e7850c0 {
  504. compatible = "aspeed,ast2600-wdt";
  505. reg = <0x1e7850C0 0x40>;
  506. status = "disabled";
  507. };
  508. peci0: peci-controller@1e78b000 {
  509. compatible = "aspeed,ast2600-peci";
  510. reg = <0x1e78b000 0x100>;
  511. interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
  512. clocks = <&syscon ASPEED_CLK_GATE_REF0CLK>;
  513. resets = <&syscon ASPEED_RESET_PECI>;
  514. cmd-timeout-ms = <1000>;
  515. clock-frequency = <1000000>;
  516. status = "disabled";
  517. };
  518. lpc: lpc@1e789000 {
  519. compatible = "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon";
  520. reg = <0x1e789000 0x1000>;
  521. reg-io-width = <4>;
  522. #address-cells = <1>;
  523. #size-cells = <1>;
  524. ranges = <0x0 0x1e789000 0x1000>;
  525. kcs1: kcs@24 {
  526. compatible = "aspeed,ast2500-kcs-bmc-v2";
  527. reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>;
  528. interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
  529. clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
  530. kcs_chan = <1>;
  531. status = "disabled";
  532. };
  533. kcs2: kcs@28 {
  534. compatible = "aspeed,ast2500-kcs-bmc-v2";
  535. reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>;
  536. interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
  537. clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
  538. status = "disabled";
  539. };
  540. kcs3: kcs@2c {
  541. compatible = "aspeed,ast2500-kcs-bmc-v2";
  542. reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>;
  543. interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
  544. clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
  545. status = "disabled";
  546. };
  547. kcs4: kcs@114 {
  548. compatible = "aspeed,ast2500-kcs-bmc-v2";
  549. reg = <0x114 0x1>, <0x118 0x1>, <0x11c 0x1>;
  550. interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
  551. clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
  552. status = "disabled";
  553. };
  554. lpc_ctrl: lpc-ctrl@80 {
  555. compatible = "aspeed,ast2600-lpc-ctrl";
  556. reg = <0x80 0x80>;
  557. clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
  558. status = "disabled";
  559. };
  560. lpc_snoop: lpc-snoop@80 {
  561. compatible = "aspeed,ast2600-lpc-snoop";
  562. reg = <0x80 0x80>;
  563. interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
  564. clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
  565. status = "disabled";
  566. };
  567. lhc: lhc@a0 {
  568. compatible = "aspeed,ast2600-lhc";
  569. reg = <0xa0 0x24 0xc8 0x8>;
  570. };
  571. lpc_reset: reset-controller@98 {
  572. compatible = "aspeed,ast2600-lpc-reset";
  573. reg = <0x98 0x4>;
  574. #reset-cells = <1>;
  575. };
  576. uart_routing: uart-routing@98 {
  577. compatible = "aspeed,ast2600-uart-routing";
  578. reg = <0x98 0x8>;
  579. status = "disabled";
  580. };
  581. ibt: ibt@140 {
  582. compatible = "aspeed,ast2600-ibt-bmc";
  583. reg = <0x140 0x18>;
  584. interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
  585. clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
  586. status = "disabled";
  587. };
  588. };
  589. sdc: sdc@1e740000 {
  590. compatible = "aspeed,ast2600-sd-controller";
  591. reg = <0x1e740000 0x100>;
  592. #address-cells = <1>;
  593. #size-cells = <1>;
  594. ranges = <0 0x1e740000 0x10000>;
  595. clocks = <&syscon ASPEED_CLK_GATE_SDCLK>;
  596. status = "disabled";
  597. sdhci0: sdhci@1e740100 {
  598. compatible = "aspeed,ast2600-sdhci", "sdhci";
  599. reg = <0x100 0x100>;
  600. interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
  601. sdhci,auto-cmd12;
  602. clocks = <&syscon ASPEED_CLK_SDIO>;
  603. status = "disabled";
  604. };
  605. sdhci1: sdhci@1e740200 {
  606. compatible = "aspeed,ast2600-sdhci", "sdhci";
  607. reg = <0x200 0x100>;
  608. interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
  609. sdhci,auto-cmd12;
  610. clocks = <&syscon ASPEED_CLK_SDIO>;
  611. status = "disabled";
  612. };
  613. };
  614. emmc_controller: sdc@1e750000 {
  615. compatible = "aspeed,ast2600-sd-controller";
  616. reg = <0x1e750000 0x100>;
  617. #address-cells = <1>;
  618. #size-cells = <1>;
  619. ranges = <0 0x1e750000 0x10000>;
  620. clocks = <&syscon ASPEED_CLK_GATE_EMMCCLK>;
  621. status = "disabled";
  622. emmc: sdhci@1e750100 {
  623. compatible = "aspeed,ast2600-sdhci";
  624. reg = <0x100 0x100>;
  625. sdhci,auto-cmd12;
  626. interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
  627. clocks = <&syscon ASPEED_CLK_EMMC>;
  628. pinctrl-names = "default";
  629. pinctrl-0 = <&pinctrl_emmc_default>;
  630. };
  631. };
  632. vuart1: serial@1e787000 {
  633. compatible = "aspeed,ast2500-vuart";
  634. reg = <0x1e787000 0x40>;
  635. reg-shift = <2>;
  636. interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
  637. clocks = <&syscon ASPEED_CLK_APB1>;
  638. no-loopback-test;
  639. status = "disabled";
  640. };
  641. vuart2: serial@1e788000 {
  642. compatible = "aspeed,ast2500-vuart";
  643. reg = <0x1e788000 0x40>;
  644. reg-shift = <2>;
  645. interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
  646. clocks = <&syscon ASPEED_CLK_APB1>;
  647. no-loopback-test;
  648. status = "disabled";
  649. };
  650. uart2: serial@1e78d000 {
  651. compatible = "ns16550a";
  652. reg = <0x1e78d000 0x20>;
  653. reg-shift = <2>;
  654. reg-io-width = <4>;
  655. interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
  656. clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
  657. resets = <&lpc_reset 5>;
  658. no-loopback-test;
  659. pinctrl-names = "default";
  660. pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>;
  661. status = "disabled";
  662. };
  663. uart3: serial@1e78e000 {
  664. compatible = "ns16550a";
  665. reg = <0x1e78e000 0x20>;
  666. reg-shift = <2>;
  667. reg-io-width = <4>;
  668. interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
  669. clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
  670. resets = <&lpc_reset 6>;
  671. no-loopback-test;
  672. pinctrl-names = "default";
  673. pinctrl-0 = <&pinctrl_txd3_default &pinctrl_rxd3_default>;
  674. status = "disabled";
  675. };
  676. uart4: serial@1e78f000 {
  677. compatible = "ns16550a";
  678. reg = <0x1e78f000 0x20>;
  679. reg-shift = <2>;
  680. reg-io-width = <4>;
  681. interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
  682. clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
  683. resets = <&lpc_reset 7>;
  684. no-loopback-test;
  685. pinctrl-names = "default";
  686. pinctrl-0 = <&pinctrl_txd4_default &pinctrl_rxd4_default>;
  687. status = "disabled";
  688. };
  689. uart6: serial@1e790000 {
  690. compatible = "ns16550a";
  691. reg = <0x1e790000 0x20>;
  692. reg-shift = <2>;
  693. reg-io-width = <4>;
  694. interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
  695. clocks = <&syscon ASPEED_CLK_GATE_UART6CLK>;
  696. no-loopback-test;
  697. pinctrl-names = "default";
  698. pinctrl-0 = <&pinctrl_uart6_default>;
  699. status = "disabled";
  700. };
  701. uart7: serial@1e790100 {
  702. compatible = "ns16550a";
  703. reg = <0x1e790100 0x20>;
  704. reg-shift = <2>;
  705. reg-io-width = <4>;
  706. interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
  707. clocks = <&syscon ASPEED_CLK_GATE_UART7CLK>;
  708. no-loopback-test;
  709. pinctrl-names = "default";
  710. pinctrl-0 = <&pinctrl_uart7_default>;
  711. status = "disabled";
  712. };
  713. uart8: serial@1e790200 {
  714. compatible = "ns16550a";
  715. reg = <0x1e790200 0x20>;
  716. reg-shift = <2>;
  717. reg-io-width = <4>;
  718. interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
  719. clocks = <&syscon ASPEED_CLK_GATE_UART8CLK>;
  720. no-loopback-test;
  721. pinctrl-names = "default";
  722. pinctrl-0 = <&pinctrl_uart8_default>;
  723. status = "disabled";
  724. };
  725. uart9: serial@1e790300 {
  726. compatible = "ns16550a";
  727. reg = <0x1e790300 0x20>;
  728. reg-shift = <2>;
  729. reg-io-width = <4>;
  730. interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
  731. clocks = <&syscon ASPEED_CLK_GATE_UART9CLK>;
  732. no-loopback-test;
  733. pinctrl-names = "default";
  734. pinctrl-0 = <&pinctrl_uart9_default>;
  735. status = "disabled";
  736. };
  737. i2c: bus@1e78a000 {
  738. compatible = "simple-bus";
  739. #address-cells = <1>;
  740. #size-cells = <1>;
  741. ranges = <0 0x1e78a000 0x1000>;
  742. };
  743. fsim0: fsi@1e79b000 {
  744. compatible = "aspeed,ast2600-fsi-master", "fsi-master";
  745. reg = <0x1e79b000 0x94>;
  746. interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
  747. pinctrl-names = "default";
  748. pinctrl-0 = <&pinctrl_fsi1_default>;
  749. clocks = <&syscon ASPEED_CLK_GATE_FSICLK>;
  750. status = "disabled";
  751. };
  752. fsim1: fsi@1e79b100 {
  753. compatible = "aspeed,ast2600-fsi-master", "fsi-master";
  754. reg = <0x1e79b100 0x94>;
  755. interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
  756. pinctrl-names = "default";
  757. pinctrl-0 = <&pinctrl_fsi2_default>;
  758. clocks = <&syscon ASPEED_CLK_GATE_FSICLK>;
  759. status = "disabled";
  760. };
  761. };
  762. };
  763. };
  764. #include "aspeed-g6-pinctrl.dtsi"
  765. &i2c {
  766. i2c0: i2c-bus@80 {
  767. #address-cells = <1>;
  768. #size-cells = <0>;
  769. #interrupt-cells = <1>;
  770. reg = <0x80 0x80>;
  771. compatible = "aspeed,ast2600-i2c-bus";
  772. clocks = <&syscon ASPEED_CLK_APB2>;
  773. resets = <&syscon ASPEED_RESET_I2C>;
  774. interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
  775. bus-frequency = <100000>;
  776. pinctrl-names = "default";
  777. pinctrl-0 = <&pinctrl_i2c1_default>;
  778. status = "disabled";
  779. };
  780. i2c1: i2c-bus@100 {
  781. #address-cells = <1>;
  782. #size-cells = <0>;
  783. #interrupt-cells = <1>;
  784. reg = <0x100 0x80>;
  785. compatible = "aspeed,ast2600-i2c-bus";
  786. clocks = <&syscon ASPEED_CLK_APB2>;
  787. resets = <&syscon ASPEED_RESET_I2C>;
  788. interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
  789. bus-frequency = <100000>;
  790. pinctrl-names = "default";
  791. pinctrl-0 = <&pinctrl_i2c2_default>;
  792. status = "disabled";
  793. };
  794. i2c2: i2c-bus@180 {
  795. #address-cells = <1>;
  796. #size-cells = <0>;
  797. #interrupt-cells = <1>;
  798. reg = <0x180 0x80>;
  799. compatible = "aspeed,ast2600-i2c-bus";
  800. clocks = <&syscon ASPEED_CLK_APB2>;
  801. resets = <&syscon ASPEED_RESET_I2C>;
  802. interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
  803. bus-frequency = <100000>;
  804. pinctrl-names = "default";
  805. pinctrl-0 = <&pinctrl_i2c3_default>;
  806. status = "disabled";
  807. };
  808. i2c3: i2c-bus@200 {
  809. #address-cells = <1>;
  810. #size-cells = <0>;
  811. #interrupt-cells = <1>;
  812. reg = <0x200 0x80>;
  813. compatible = "aspeed,ast2600-i2c-bus";
  814. clocks = <&syscon ASPEED_CLK_APB2>;
  815. resets = <&syscon ASPEED_RESET_I2C>;
  816. interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
  817. bus-frequency = <100000>;
  818. pinctrl-names = "default";
  819. pinctrl-0 = <&pinctrl_i2c4_default>;
  820. status = "disabled";
  821. };
  822. i2c4: i2c-bus@280 {
  823. #address-cells = <1>;
  824. #size-cells = <0>;
  825. #interrupt-cells = <1>;
  826. reg = <0x280 0x80>;
  827. compatible = "aspeed,ast2600-i2c-bus";
  828. clocks = <&syscon ASPEED_CLK_APB2>;
  829. resets = <&syscon ASPEED_RESET_I2C>;
  830. interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
  831. bus-frequency = <100000>;
  832. pinctrl-names = "default";
  833. pinctrl-0 = <&pinctrl_i2c5_default>;
  834. status = "disabled";
  835. };
  836. i2c5: i2c-bus@300 {
  837. #address-cells = <1>;
  838. #size-cells = <0>;
  839. #interrupt-cells = <1>;
  840. reg = <0x300 0x80>;
  841. compatible = "aspeed,ast2600-i2c-bus";
  842. clocks = <&syscon ASPEED_CLK_APB2>;
  843. resets = <&syscon ASPEED_RESET_I2C>;
  844. interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
  845. bus-frequency = <100000>;
  846. pinctrl-names = "default";
  847. pinctrl-0 = <&pinctrl_i2c6_default>;
  848. status = "disabled";
  849. };
  850. i2c6: i2c-bus@380 {
  851. #address-cells = <1>;
  852. #size-cells = <0>;
  853. #interrupt-cells = <1>;
  854. reg = <0x380 0x80>;
  855. compatible = "aspeed,ast2600-i2c-bus";
  856. clocks = <&syscon ASPEED_CLK_APB2>;
  857. resets = <&syscon ASPEED_RESET_I2C>;
  858. interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
  859. bus-frequency = <100000>;
  860. pinctrl-names = "default";
  861. pinctrl-0 = <&pinctrl_i2c7_default>;
  862. status = "disabled";
  863. };
  864. i2c7: i2c-bus@400 {
  865. #address-cells = <1>;
  866. #size-cells = <0>;
  867. #interrupt-cells = <1>;
  868. reg = <0x400 0x80>;
  869. compatible = "aspeed,ast2600-i2c-bus";
  870. clocks = <&syscon ASPEED_CLK_APB2>;
  871. resets = <&syscon ASPEED_RESET_I2C>;
  872. interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
  873. bus-frequency = <100000>;
  874. pinctrl-names = "default";
  875. pinctrl-0 = <&pinctrl_i2c8_default>;
  876. status = "disabled";
  877. };
  878. i2c8: i2c-bus@480 {
  879. #address-cells = <1>;
  880. #size-cells = <0>;
  881. #interrupt-cells = <1>;
  882. reg = <0x480 0x80>;
  883. compatible = "aspeed,ast2600-i2c-bus";
  884. clocks = <&syscon ASPEED_CLK_APB2>;
  885. resets = <&syscon ASPEED_RESET_I2C>;
  886. interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
  887. bus-frequency = <100000>;
  888. pinctrl-names = "default";
  889. pinctrl-0 = <&pinctrl_i2c9_default>;
  890. status = "disabled";
  891. };
  892. i2c9: i2c-bus@500 {
  893. #address-cells = <1>;
  894. #size-cells = <0>;
  895. #interrupt-cells = <1>;
  896. reg = <0x500 0x80>;
  897. compatible = "aspeed,ast2600-i2c-bus";
  898. clocks = <&syscon ASPEED_CLK_APB2>;
  899. resets = <&syscon ASPEED_RESET_I2C>;
  900. interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
  901. bus-frequency = <100000>;
  902. pinctrl-names = "default";
  903. pinctrl-0 = <&pinctrl_i2c10_default>;
  904. status = "disabled";
  905. };
  906. i2c10: i2c-bus@580 {
  907. #address-cells = <1>;
  908. #size-cells = <0>;
  909. #interrupt-cells = <1>;
  910. reg = <0x580 0x80>;
  911. compatible = "aspeed,ast2600-i2c-bus";
  912. clocks = <&syscon ASPEED_CLK_APB2>;
  913. resets = <&syscon ASPEED_RESET_I2C>;
  914. interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
  915. bus-frequency = <100000>;
  916. pinctrl-names = "default";
  917. pinctrl-0 = <&pinctrl_i2c11_default>;
  918. status = "disabled";
  919. };
  920. i2c11: i2c-bus@600 {
  921. #address-cells = <1>;
  922. #size-cells = <0>;
  923. #interrupt-cells = <1>;
  924. reg = <0x600 0x80>;
  925. compatible = "aspeed,ast2600-i2c-bus";
  926. clocks = <&syscon ASPEED_CLK_APB2>;
  927. resets = <&syscon ASPEED_RESET_I2C>;
  928. interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
  929. bus-frequency = <100000>;
  930. pinctrl-names = "default";
  931. pinctrl-0 = <&pinctrl_i2c12_default>;
  932. status = "disabled";
  933. };
  934. i2c12: i2c-bus@680 {
  935. #address-cells = <1>;
  936. #size-cells = <0>;
  937. #interrupt-cells = <1>;
  938. reg = <0x680 0x80>;
  939. compatible = "aspeed,ast2600-i2c-bus";
  940. clocks = <&syscon ASPEED_CLK_APB2>;
  941. resets = <&syscon ASPEED_RESET_I2C>;
  942. interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
  943. bus-frequency = <100000>;
  944. pinctrl-names = "default";
  945. pinctrl-0 = <&pinctrl_i2c13_default>;
  946. status = "disabled";
  947. };
  948. i2c13: i2c-bus@700 {
  949. #address-cells = <1>;
  950. #size-cells = <0>;
  951. #interrupt-cells = <1>;
  952. reg = <0x700 0x80>;
  953. compatible = "aspeed,ast2600-i2c-bus";
  954. clocks = <&syscon ASPEED_CLK_APB2>;
  955. resets = <&syscon ASPEED_RESET_I2C>;
  956. interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
  957. bus-frequency = <100000>;
  958. pinctrl-names = "default";
  959. pinctrl-0 = <&pinctrl_i2c14_default>;
  960. status = "disabled";
  961. };
  962. i2c14: i2c-bus@780 {
  963. #address-cells = <1>;
  964. #size-cells = <0>;
  965. #interrupt-cells = <1>;
  966. reg = <0x780 0x80>;
  967. compatible = "aspeed,ast2600-i2c-bus";
  968. clocks = <&syscon ASPEED_CLK_APB2>;
  969. resets = <&syscon ASPEED_RESET_I2C>;
  970. interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
  971. bus-frequency = <100000>;
  972. pinctrl-names = "default";
  973. pinctrl-0 = <&pinctrl_i2c15_default>;
  974. status = "disabled";
  975. };
  976. i2c15: i2c-bus@800 {
  977. #address-cells = <1>;
  978. #size-cells = <0>;
  979. #interrupt-cells = <1>;
  980. reg = <0x800 0x80>;
  981. compatible = "aspeed,ast2600-i2c-bus";
  982. clocks = <&syscon ASPEED_CLK_APB2>;
  983. resets = <&syscon ASPEED_RESET_I2C>;
  984. interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
  985. bus-frequency = <100000>;
  986. pinctrl-names = "default";
  987. pinctrl-0 = <&pinctrl_i2c16_default>;
  988. status = "disabled";
  989. };
  990. };