aspeed-bmc-ampere-mtmitchell.dts 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. // Copyright (c) 2022, Ampere Computing LLC
  3. /dts-v1/;
  4. #include "aspeed-g6.dtsi"
  5. #include <dt-bindings/gpio/aspeed-gpio.h>
  6. / {
  7. model = "Ampere Mt.Mitchell BMC";
  8. compatible = "ampere,mtmitchell-bmc", "aspeed,ast2600";
  9. chosen {
  10. stdout-path = &uart5;
  11. };
  12. memory@80000000 {
  13. device_type = "memory";
  14. reg = <0x80000000 0x80000000>;
  15. };
  16. reserved-memory {
  17. #address-cells = <1>;
  18. #size-cells = <1>;
  19. ranges;
  20. gfx_memory: framebuffer {
  21. size = <0x01000000>;
  22. alignment = <0x01000000>;
  23. compatible = "shared-dma-pool";
  24. reusable;
  25. };
  26. video_engine_memory: video {
  27. size = <0x04000000>;
  28. alignment = <0x01000000>;
  29. compatible = "shared-dma-pool";
  30. reusable;
  31. };
  32. vga_memory: region@bf000000 {
  33. no-map;
  34. compatible = "shared-dma-pool";
  35. reg = <0xbf000000 0x01000000>; /* 16M */
  36. };
  37. };
  38. voltage_mon_reg: voltage-mon-regulator {
  39. compatible = "regulator-fixed";
  40. regulator-name = "ltc2497_reg";
  41. regulator-min-microvolt = <3300000>;
  42. regulator-max-microvolt = <3300000>;
  43. regulator-always-on;
  44. };
  45. gpioI5mux: mux-controller {
  46. compatible = "gpio-mux";
  47. #mux-control-cells = <0>;
  48. mux-gpios = <&gpio0 ASPEED_GPIO(I, 5) GPIO_ACTIVE_HIGH>;
  49. };
  50. adc0mux: adc0mux {
  51. compatible = "io-channel-mux";
  52. io-channels = <&adc0 0>;
  53. #io-channel-cells = <1>;
  54. io-channel-names = "parent";
  55. mux-controls = <&gpioI5mux>;
  56. channels = "s0", "s1";
  57. };
  58. adc1mux: adc1mux {
  59. compatible = "io-channel-mux";
  60. io-channels = <&adc0 1>;
  61. #io-channel-cells = <1>;
  62. io-channel-names = "parent";
  63. mux-controls = <&gpioI5mux>;
  64. channels = "s0", "s1";
  65. };
  66. adc2mux: adc2mux {
  67. compatible = "io-channel-mux";
  68. io-channels = <&adc0 2>;
  69. #io-channel-cells = <1>;
  70. io-channel-names = "parent";
  71. mux-controls = <&gpioI5mux>;
  72. channels = "s0", "s1";
  73. };
  74. adc3mux: adc3mux {
  75. compatible = "io-channel-mux";
  76. io-channels = <&adc0 3>;
  77. #io-channel-cells = <1>;
  78. io-channel-names = "parent";
  79. mux-controls = <&gpioI5mux>;
  80. channels = "s0", "s1";
  81. };
  82. adc4mux: adc4mux {
  83. compatible = "io-channel-mux";
  84. io-channels = <&adc0 4>;
  85. #io-channel-cells = <1>;
  86. io-channel-names = "parent";
  87. mux-controls = <&gpioI5mux>;
  88. channels = "s0", "s1";
  89. };
  90. adc5mux: adc5mux {
  91. compatible = "io-channel-mux";
  92. io-channels = <&adc0 5>;
  93. #io-channel-cells = <1>;
  94. io-channel-names = "parent";
  95. mux-controls = <&gpioI5mux>;
  96. channels = "s0", "s1";
  97. };
  98. adc6mux: adc6mux {
  99. compatible = "io-channel-mux";
  100. io-channels = <&adc0 6>;
  101. #io-channel-cells = <1>;
  102. io-channel-names = "parent";
  103. mux-controls = <&gpioI5mux>;
  104. channels = "s0", "s1";
  105. };
  106. adc7mux: adc7mux {
  107. compatible = "io-channel-mux";
  108. io-channels = <&adc0 7>;
  109. #io-channel-cells = <1>;
  110. io-channel-names = "parent";
  111. mux-controls = <&gpioI5mux>;
  112. channels = "s0", "s1";
  113. };
  114. adc8mux: adc8mux {
  115. compatible = "io-channel-mux";
  116. io-channels = <&adc1 0>;
  117. #io-channel-cells = <1>;
  118. io-channel-names = "parent";
  119. mux-controls = <&gpioI5mux>;
  120. channels = "s0", "s1";
  121. };
  122. adc9mux: adc9mux {
  123. compatible = "io-channel-mux";
  124. io-channels = <&adc1 1>;
  125. #io-channel-cells = <1>;
  126. io-channel-names = "parent";
  127. mux-controls = <&gpioI5mux>;
  128. channels = "s0", "s1";
  129. };
  130. adc10mux: adc10mux {
  131. compatible = "io-channel-mux";
  132. io-channels = <&adc1 2>;
  133. #io-channel-cells = <1>;
  134. io-channel-names = "parent";
  135. mux-controls = <&gpioI5mux>;
  136. channels = "s0", "s1";
  137. };
  138. adc11mux: adc11mux {
  139. compatible = "io-channel-mux";
  140. io-channels = <&adc1 3>;
  141. #io-channel-cells = <1>;
  142. io-channel-names = "parent";
  143. mux-controls = <&gpioI5mux>;
  144. channels = "s0", "s1";
  145. };
  146. adc12mux: adc12mux {
  147. compatible = "io-channel-mux";
  148. io-channels = <&adc1 4>;
  149. #io-channel-cells = <1>;
  150. io-channel-names = "parent";
  151. mux-controls = <&gpioI5mux>;
  152. channels = "s0", "s1";
  153. };
  154. adc13mux: adc13mux {
  155. compatible = "io-channel-mux";
  156. io-channels = <&adc1 5>;
  157. #io-channel-cells = <1>;
  158. io-channel-names = "parent";
  159. mux-controls = <&gpioI5mux>;
  160. channels = "s0", "s1";
  161. };
  162. adc14mux: adc14mux {
  163. compatible = "io-channel-mux";
  164. io-channels = <&adc1 6>;
  165. #io-channel-cells = <1>;
  166. io-channel-names = "parent";
  167. mux-controls = <&gpioI5mux>;
  168. channels = "s0", "s1";
  169. };
  170. adc15mux: adc15mux {
  171. compatible = "io-channel-mux";
  172. io-channels = <&adc1 7>;
  173. #io-channel-cells = <1>;
  174. io-channel-names = "parent";
  175. mux-controls = <&gpioI5mux>;
  176. channels = "s0", "s1";
  177. };
  178. iio-hwmon {
  179. compatible = "iio-hwmon";
  180. io-channels = <&adc0mux 0>, <&adc0mux 1>,
  181. <&adc1mux 0>, <&adc1mux 1>,
  182. <&adc2mux 0>, <&adc2mux 1>,
  183. <&adc3mux 0>, <&adc3mux 1>,
  184. <&adc4mux 0>, <&adc4mux 1>,
  185. <&adc5mux 0>, <&adc5mux 1>,
  186. <&adc6mux 0>, <&adc6mux 1>,
  187. <&adc7mux 0>, <&adc7mux 1>,
  188. <&adc8mux 0>, <&adc8mux 1>,
  189. <&adc9mux 0>, <&adc9mux 1>,
  190. <&adc10mux 0>, <&adc10mux 1>,
  191. <&adc11mux 0>, <&adc11mux 1>,
  192. <&adc12mux 0>, <&adc12mux 1>,
  193. <&adc13mux 0>, <&adc13mux 1>,
  194. <&adc14mux 0>, <&adc14mux 1>,
  195. <&adc15mux 0>, <&adc15mux 1>,
  196. <&adc_i2c 0>, <&adc_i2c 1>,
  197. <&adc_i2c 2>, <&adc_i2c 3>,
  198. <&adc_i2c 4>, <&adc_i2c 5>,
  199. <&adc_i2c 6>, <&adc_i2c 7>,
  200. <&adc_i2c 8>, <&adc_i2c 9>,
  201. <&adc_i2c 10>, <&adc_i2c 11>,
  202. <&adc_i2c 12>, <&adc_i2c 13>,
  203. <&adc_i2c 14>, <&adc_i2c 15>;
  204. };
  205. };
  206. &mdio0 {
  207. status = "okay";
  208. ethphy0: ethernet-phy@0 {
  209. compatible = "ethernet-phy-ieee802.3-c22";
  210. reg = <0>;
  211. };
  212. };
  213. &mac0 {
  214. status = "okay";
  215. phy-mode = "rgmii";
  216. phy-handle = <&ethphy0>;
  217. pinctrl-names = "default";
  218. pinctrl-0 = <&pinctrl_rgmii1_default>;
  219. };
  220. &fmc {
  221. status = "okay";
  222. flash@0 {
  223. status = "okay";
  224. m25p,fast-read;
  225. label = "bmc";
  226. spi-max-frequency = <50000000>;
  227. #include "openbmc-flash-layout-64.dtsi"
  228. };
  229. flash@1 {
  230. status = "okay";
  231. m25p,fast-read;
  232. label = "alt-bmc";
  233. spi-max-frequency = <50000000>;
  234. #include "openbmc-flash-layout-64-alt.dtsi"
  235. };
  236. };
  237. &spi1 {
  238. status = "okay";
  239. pinctrl-names = "default";
  240. pinctrl-0 = <&pinctrl_spi1_default>;
  241. flash@0 {
  242. status = "okay";
  243. m25p,fast-read;
  244. label = "pnor";
  245. spi-max-frequency = <20000000>;
  246. };
  247. };
  248. &uart1 {
  249. status = "okay";
  250. };
  251. &uart2 {
  252. status = "okay";
  253. };
  254. &uart3 {
  255. status = "okay";
  256. };
  257. &uart4 {
  258. status = "okay";
  259. };
  260. &i2c0 {
  261. status = "okay";
  262. temperature-sensor@2e {
  263. compatible = "adi,adt7490";
  264. reg = <0x2e>;
  265. };
  266. };
  267. &i2c1 {
  268. status = "okay";
  269. };
  270. &i2c2 {
  271. status = "okay";
  272. psu@58 {
  273. compatible = "pmbus";
  274. reg = <0x58>;
  275. };
  276. psu@59 {
  277. compatible = "pmbus";
  278. reg = <0x59>;
  279. };
  280. };
  281. &i2c3 {
  282. status = "okay";
  283. };
  284. &i2c4 {
  285. status = "okay";
  286. adc_i2c: adc@16 {
  287. compatible = "lltc,ltc2497";
  288. reg = <0x16>;
  289. vref-supply = <&voltage_mon_reg>;
  290. #io-channel-cells = <1>;
  291. };
  292. eeprom@50 {
  293. compatible = "atmel,24c64";
  294. reg = <0x50>;
  295. pagesize = <32>;
  296. };
  297. i2c-mux@70 {
  298. compatible = "nxp,pca9545";
  299. #address-cells = <1>;
  300. #size-cells = <0>;
  301. reg = <0x70>;
  302. i2c-mux-idle-disconnect;
  303. i2c4_bus70_chn0: i2c@0 {
  304. #address-cells = <1>;
  305. #size-cells = <0>;
  306. reg = <0x0>;
  307. outlet_temp1: temperature-sensor@48 {
  308. compatible = "ti,tmp75";
  309. reg = <0x48>;
  310. };
  311. psu1_inlet_temp2: temperature-sensor@49 {
  312. compatible = "ti,tmp75";
  313. reg = <0x49>;
  314. };
  315. };
  316. i2c4_bus70_chn1: i2c@1 {
  317. #address-cells = <1>;
  318. #size-cells = <0>;
  319. reg = <0x1>;
  320. pcie_zone_temp1: temperature-sensor@48 {
  321. compatible = "ti,tmp75";
  322. reg = <0x48>;
  323. };
  324. psu0_inlet_temp2: temperature-sensor@49 {
  325. compatible = "ti,tmp75";
  326. reg = <0x49>;
  327. };
  328. };
  329. i2c4_bus70_chn2: i2c@2 {
  330. #address-cells = <1>;
  331. #size-cells = <0>;
  332. reg = <0x2>;
  333. pcie_zone_temp2: temperature-sensor@48 {
  334. compatible = "ti,tmp75";
  335. reg = <0x48>;
  336. };
  337. outlet_temp2: temperature-sensor@49 {
  338. compatible = "ti,tmp75";
  339. reg = <0x49>;
  340. };
  341. };
  342. i2c4_bus70_chn3: i2c@3 {
  343. #address-cells = <1>;
  344. #size-cells = <0>;
  345. reg = <0x3>;
  346. mb_inlet_temp1: temperature-sensor@7c {
  347. compatible = "microchip,emc1413";
  348. reg = <0x7c>;
  349. };
  350. mb_inlet_temp2: temperature-sensor@4c {
  351. compatible = "microchip,emc1413";
  352. reg = <0x4c>;
  353. };
  354. };
  355. };
  356. };
  357. &i2c5 {
  358. status = "okay";
  359. i2c-mux@70 {
  360. compatible = "nxp,pca9548";
  361. #address-cells = <1>;
  362. #size-cells = <0>;
  363. reg = <0x70>;
  364. i2c-mux-idle-disconnect;
  365. };
  366. };
  367. &i2c6 {
  368. status = "okay";
  369. rtc@51 {
  370. compatible = "nxp,pcf85063a";
  371. reg = <0x51>;
  372. };
  373. };
  374. &i2c7 {
  375. status = "okay";
  376. };
  377. &i2c9 {
  378. status = "okay";
  379. };
  380. &i2c11 {
  381. status = "okay";
  382. };
  383. &i2c14 {
  384. status = "okay";
  385. eeprom@50 {
  386. compatible = "atmel,24c64";
  387. reg = <0x50>;
  388. pagesize = <32>;
  389. };
  390. bmc_ast2600_cpu: temperature-sensor@35 {
  391. compatible = "ti,tmp175";
  392. reg = <0x35>;
  393. };
  394. };
  395. &adc0 {
  396. ref_voltage = <2500>;
  397. status = "okay";
  398. pinctrl-names = "default";
  399. pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default
  400. &pinctrl_adc2_default &pinctrl_adc3_default
  401. &pinctrl_adc4_default &pinctrl_adc5_default
  402. &pinctrl_adc6_default &pinctrl_adc7_default>;
  403. };
  404. &adc1 {
  405. ref_voltage = <2500>;
  406. status = "okay";
  407. pinctrl-names = "default";
  408. pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default
  409. &pinctrl_adc10_default &pinctrl_adc11_default
  410. &pinctrl_adc12_default &pinctrl_adc13_default
  411. &pinctrl_adc14_default &pinctrl_adc15_default>;
  412. };
  413. &vhub {
  414. status = "okay";
  415. };
  416. &video {
  417. status = "okay";
  418. memory-region = <&video_engine_memory>;
  419. };
  420. &gpio0 {
  421. gpio-line-names =
  422. /*A0-A7*/ "","","","","","i2c2-reset-n","i2c6-reset-n","i2c4-reset-n",
  423. /*B0-B7*/ "","","","","host0-sysreset-n","host0-pmin-n","","",
  424. /*C0-C7*/ "s0-vrd-fault-n","s1-vrd-fault-n","","",
  425. "irq-n","","vrd-sel","spd-sel",
  426. /*D0-D7*/ "presence-ps0","presence-ps1","hsc-12vmain-alt2-n","ext-high-temp-n",
  427. "","bmc-ncsi-txen","","",
  428. /*E0-E7*/ "","","clk50m-bmc-ncsi","","","","","",
  429. /*F0-F7*/ "s0-pcp-oc-warn-n","s1-pcp-oc-warn-n","power-chassis-control",
  430. "cpu-bios-recover","s0-heartbeat","hs-csout-prochot",
  431. "s0-vr-hot-n","s1-vr-hot-n",
  432. /*G0-G7*/ "","","hsc-12vmain-alt1-n","","","","","",
  433. /*H0-H7*/ "","","wd-disable-n","power-chassis-good","","","","",
  434. /*I0-I7*/ "","","","","","adc-sw","power-button","rtc-battery-voltage-read-enable",
  435. /*J0-J7*/ "","","","","","","","",
  436. /*K0-K7*/ "","","","","","","","",
  437. /*L0-L7*/ "","","","","","","","",
  438. /*M0-M7*/ "","s0-ddr-save","soc-spi-nor-access","presence-cpu0",
  439. "s0-rtc-lock","","","",
  440. /*N0-N7*/ "hpm-fw-recovery","hpm-stby-rst-n","jtag-sel-s0","led-sw-hb",
  441. "jtag-dbgr-prsnt-n","s1-heartbeat","","",
  442. /*O0-O7*/ "","","","","","","","",
  443. /*P0-P7*/ "ps0-ac-loss-n","ps1-ac-loss-n","","",
  444. "led-fault","cpld-user-mode","jtag-srst-n","led-bmc-hb",
  445. /*Q0-Q7*/ "","","","","","","","",
  446. /*R0-R7*/ "","","","","","","","",
  447. /*S0-S7*/ "","","identify-button","led-identify",
  448. "s1-ddr-save","spi-nor-access","sys-pgood","presence-cpu1",
  449. /*T0-T7*/ "","","","","","","","",
  450. /*U0-U7*/ "","","","","","","","",
  451. /*V0-V7*/ "s0-hightemp-n","s0-fault-alert","s0-sys-auth-failure-n",
  452. "host0-reboot-ack-n","host0-ready","host0-shd-req-n",
  453. "host0-shd-ack-n","s0-overtemp-n",
  454. /*W0-W7*/ "ocp-aux-pwren","ocp-main-pwren","ocp-pgood","",
  455. "bmc-ok","bmc-ready","spi0-program-sel","spi0-backup-sel",
  456. /*X0-X7*/ "i2c-backup-sel","s1-fault-alert","s1-fw-boot-ok",
  457. "s1-hightemp-n","s0-spi-auth-fail-n","s1-sys-auth-failure-n",
  458. "s1-overtemp-n","s1-spi-auth-fail-n",
  459. /*Y0-Y7*/ "","","","","","","","host0-special-boot",
  460. /*Z0-Z7*/ "reset-button","ps0-pgood","ps1-pgood","","","","","";
  461. };
  462. &gpio1 {
  463. gpio-line-names =
  464. /*18A0-18A7*/ "","","","","","","","",
  465. /*18B0-18B7*/ "","","","","","","s0-soc-pgood","",
  466. /*18C0-18C7*/ "uart1-mode0","uart1-mode1","uart2-mode0","uart2-mode1",
  467. "uart3-mode0","uart3-mode1","uart4-mode0","uart4-mode1",
  468. /*18D0-18D7*/ "","","","","","","","",
  469. /*18E0-18E3*/ "","","","";
  470. };