armada-xp-db-dxbc2.dts 2.4 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Device Tree file for DB-DXBC2 board
  4. *
  5. * Copyright (C) 2016 Allied Telesis Labs
  6. *
  7. * Based on armada-xp-db.dts
  8. *
  9. * Note: this Device Tree assumes that the bootloader has remapped the
  10. * internal registers to 0xf1000000 (instead of the default
  11. * 0xd0000000). The 0xf1000000 is the default used by the recent,
  12. * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
  13. * boards were delivered with an older version of the bootloader that
  14. * left internal registers mapped at 0xd0000000. If you are in this
  15. * situation, you should either update your bootloader (preferred
  16. * solution) or the below Device Tree should be adjusted.
  17. */
  18. /dts-v1/;
  19. #include "armada-xp-98dx4251.dtsi"
  20. / {
  21. model = "Marvell Bobcat2 Evaluation Board";
  22. compatible = "marvell,db-dxbc2", "marvell,armadaxp-98dx4251", "marvell,armada-370-xp";
  23. chosen {
  24. bootargs = "console=ttyS0,115200 earlyprintk";
  25. };
  26. memory {
  27. device_type = "memory";
  28. reg = <0 0x00000000 0 0x20000000>; /* 512 MB */
  29. };
  30. };
  31. &devbus_bootcs {
  32. status = "okay";
  33. /* Device Bus parameters are required */
  34. /* Read parameters */
  35. devbus,bus-width = <16>;
  36. devbus,turn-off-ps = <60000>;
  37. devbus,badr-skew-ps = <0>;
  38. devbus,acc-first-ps = <124000>;
  39. devbus,acc-next-ps = <248000>;
  40. devbus,rd-setup-ps = <0>;
  41. devbus,rd-hold-ps = <0>;
  42. /* Write parameters */
  43. devbus,sync-enable = <0>;
  44. devbus,wr-high-ps = <60000>;
  45. devbus,wr-low-ps = <60000>;
  46. devbus,ale-wr-ps = <60000>;
  47. };
  48. &i2c0 {
  49. clock-frequency = <100000>;
  50. status = "okay";
  51. };
  52. &uart0 {
  53. status = "okay";
  54. };
  55. &uart1 {
  56. status = "okay";
  57. };
  58. &nand_controller {
  59. status = "okay";
  60. nand@0 {
  61. reg = <0>;
  62. label = "pxa3xx_nand-0";
  63. nand-rb = <0>;
  64. marvell,nand-keep-config;
  65. nand-on-flash-bbt;
  66. nand-ecc-strength = <4>;
  67. nand-ecc-step-size = <512>;
  68. };
  69. };
  70. &sdio {
  71. pinctrl-0 = <&sdio_pins>;
  72. pinctrl-names = "default";
  73. status = "okay";
  74. /* No CD or WP GPIOs */
  75. broken-cd;
  76. };
  77. &spi0 {
  78. status = "okay";
  79. flash@0 {
  80. #address-cells = <1>;
  81. #size-cells = <1>;
  82. compatible = "m25p64";
  83. reg = <0>; /* Chip select 0 */
  84. spi-max-frequency = <20000000>;
  85. m25p,fast-read;
  86. partition@u-boot {
  87. reg = <0x00000000 0x00100000>;
  88. label = "u-boot";
  89. };
  90. partition@u-boot-env {
  91. reg = <0x00100000 0x00040000>;
  92. label = "u-boot-env";
  93. };
  94. partition@unused {
  95. reg = <0x00140000 0x00ec0000>;
  96. label = "unused";
  97. };
  98. };
  99. };