armada-395-gp.dts 2.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136
  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /*
  3. * Device Tree file for Marvell Armada 395 GP board
  4. *
  5. * Copyright (C) 2016 Marvell
  6. *
  7. * Grzegorz Jaszczyk <[email protected]>
  8. */
  9. /dts-v1/;
  10. #include "armada-395.dtsi"
  11. / {
  12. model = "Marvell Armada 395 GP Board";
  13. compatible = "marvell,a395-gp", "marvell,armada395",
  14. "marvell,armada390";
  15. chosen {
  16. stdout-path = "serial0:115200n8";
  17. };
  18. memory {
  19. device_type = "memory";
  20. reg = <0x00000000 0x40000000>; /* 1 GB */
  21. };
  22. soc {
  23. ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
  24. MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
  25. internal-regs {
  26. i2c@11000 {
  27. status = "okay";
  28. clock-frequency = <100000>;
  29. eeprom@57 {
  30. compatible = "atmel,24c64";
  31. reg = <0x57>;
  32. };
  33. };
  34. serial@12000 {
  35. /*
  36. * Exported on the micro USB connector CON17
  37. * through an FTDI
  38. */
  39. status = "okay";
  40. };
  41. /* CON1 */
  42. usb@58000 {
  43. status = "okay";
  44. };
  45. /* CON2 */
  46. sata@a8000 {
  47. status = "okay";
  48. };
  49. /* CON18 */
  50. sdhci@d8000 {
  51. clock-frequency = <200000000>;
  52. broken-cd;
  53. wp-inverted;
  54. bus-width = <8>;
  55. status = "okay";
  56. no-1-8-v;
  57. };
  58. /* CON4 */
  59. usb3@f0000 {
  60. status = "okay";
  61. };
  62. };
  63. pcie {
  64. status = "okay";
  65. /*
  66. * The two PCIe units are accessible through
  67. * mini PCIe slot on the board.
  68. */
  69. /* CON7 */
  70. pcie@2,0 {
  71. /* Port 1, Lane 0 */
  72. status = "okay";
  73. };
  74. /* CON8 */
  75. pcie@4,0 {
  76. /* Port 3, Lane 0 */
  77. status = "okay";
  78. };
  79. };
  80. };
  81. };
  82. &nand_controller {
  83. status = "okay";
  84. pinctrl-0 = <&nand_pins>;
  85. pinctrl-names = "default";
  86. nand@0 {
  87. reg = <0>;
  88. label = "pxa3xx_nand-0";
  89. nand-rb = <0>;
  90. marvell,nand-keep-config;
  91. nand-on-flash-bbt;
  92. nand-ecc-strength = <4>;
  93. nand-ecc-step-size = <512>;
  94. partitions {
  95. compatible = "fixed-partitions";
  96. #address-cells = <1>;
  97. #size-cells = <1>;
  98. partition@0 {
  99. label = "U-Boot";
  100. reg = <0x00000000 0x00600000>;
  101. read-only;
  102. };
  103. partition@800000 {
  104. label = "uImage";
  105. reg = <0x00600000 0x00400000>;
  106. read-only;
  107. };
  108. partition@1000000 {
  109. label = "Root";
  110. reg = <0x00a00000 0x3f600000>;
  111. };
  112. };
  113. };
  114. };