armada-388-clearfog.dtsi 4.8 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /*
  3. * Device Tree include file for SolidRun Clearfog 88F6828 based boards
  4. *
  5. * Copyright (C) 2015 Russell King
  6. */
  7. #include "armada-388.dtsi"
  8. #include "armada-38x-solidrun-microsom.dtsi"
  9. / {
  10. aliases {
  11. /* So that mvebu u-boot can update the MAC addresses */
  12. ethernet1 = &eth0;
  13. ethernet2 = &eth1;
  14. ethernet3 = &eth2;
  15. };
  16. chosen {
  17. stdout-path = "serial0:115200n8";
  18. };
  19. reg_3p3v: regulator-3p3v {
  20. compatible = "regulator-fixed";
  21. regulator-name = "3P3V";
  22. regulator-min-microvolt = <3300000>;
  23. regulator-max-microvolt = <3300000>;
  24. regulator-always-on;
  25. };
  26. soc {
  27. internal-regs {
  28. sata@a8000 {
  29. /* pinctrl? */
  30. status = "okay";
  31. };
  32. sata@e0000 {
  33. /* pinctrl? */
  34. status = "okay";
  35. };
  36. sdhci@d8000 {
  37. bus-width = <4>;
  38. cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
  39. no-1-8-v;
  40. pinctrl-0 = <&microsom_sdhci_pins
  41. &clearfog_sdhci_cd_pins>;
  42. pinctrl-names = "default";
  43. status = "okay";
  44. vmmc-supply = <&reg_3p3v>;
  45. wp-inverted;
  46. };
  47. usb@58000 {
  48. /* CON3, nearest power. */
  49. status = "okay";
  50. };
  51. usb3@f8000 {
  52. /* CON7 */
  53. status = "okay";
  54. };
  55. };
  56. pcie {
  57. status = "okay";
  58. /*
  59. * The two PCIe units are accessible through
  60. * the mini-PCIe connectors on the board.
  61. */
  62. pcie@2,0 {
  63. /* Port 1, Lane 0. CON3, nearest power. */
  64. reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
  65. status = "okay";
  66. };
  67. };
  68. };
  69. sfp: sfp {
  70. compatible = "sff,sfp";
  71. i2c-bus = <&i2c1>;
  72. los-gpio = <&expander0 12 GPIO_ACTIVE_HIGH>;
  73. mod-def0-gpio = <&expander0 15 GPIO_ACTIVE_LOW>;
  74. tx-disable-gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
  75. tx-fault-gpio = <&expander0 13 GPIO_ACTIVE_HIGH>;
  76. maximum-power-milliwatt = <2000>;
  77. };
  78. };
  79. &eth1 {
  80. /* ethernet@30000 */
  81. bm,pool-long = <2>;
  82. bm,pool-short = <1>;
  83. buffer-manager = <&bm>;
  84. phys = <&comphy1 1>;
  85. phy-mode = "sgmii";
  86. status = "okay";
  87. };
  88. &eth2 {
  89. /* ethernet@34000 */
  90. bm,pool-long = <3>;
  91. bm,pool-short = <1>;
  92. buffer-manager = <&bm>;
  93. managed = "in-band-status";
  94. phys = <&comphy5 2>;
  95. phy-mode = "sgmii";
  96. sfp = <&sfp>;
  97. status = "okay";
  98. };
  99. &i2c0 {
  100. /*
  101. * PCA9655 GPIO expander, up to 1MHz clock.
  102. * 0-CON3 CLKREQ#
  103. * 1-CON3 PERST#
  104. * 2-
  105. * 3-CON3 W_DISABLE
  106. * 4-
  107. * 5-USB3 overcurrent
  108. * 6-USB3 power
  109. * 7-
  110. * 8-JP4 P1
  111. * 9-JP4 P4
  112. * 10-JP4 P5
  113. * 11-m.2 DEVSLP
  114. * 12-SFP_LOS
  115. * 13-SFP_TX_FAULT
  116. * 14-SFP_TX_DISABLE
  117. * 15-SFP_MOD_DEF0
  118. */
  119. expander0: gpio-expander@20 {
  120. /*
  121. * This is how it should be:
  122. * compatible = "onnn,pca9655", "nxp,pca9555";
  123. * but you can't do this because of the way I2C works.
  124. */
  125. compatible = "nxp,pca9555";
  126. gpio-controller;
  127. #gpio-cells = <2>;
  128. reg = <0x20>;
  129. pcie1-0-clkreq-hog {
  130. gpio-hog;
  131. gpios = <0 GPIO_ACTIVE_LOW>;
  132. input;
  133. line-name = "pcie1.0-clkreq";
  134. };
  135. pcie1-0-w-disable-hog {
  136. gpio-hog;
  137. gpios = <3 GPIO_ACTIVE_LOW>;
  138. output-low;
  139. line-name = "pcie1.0-w-disable";
  140. };
  141. usb3-ilimit-hog {
  142. gpio-hog;
  143. gpios = <5 GPIO_ACTIVE_LOW>;
  144. input;
  145. line-name = "usb3-current-limit";
  146. };
  147. usb3-power-hog {
  148. gpio-hog;
  149. gpios = <6 GPIO_ACTIVE_HIGH>;
  150. output-high;
  151. line-name = "usb3-power";
  152. };
  153. m2-devslp-hog {
  154. gpio-hog;
  155. gpios = <11 GPIO_ACTIVE_HIGH>;
  156. output-low;
  157. line-name = "m.2 devslp";
  158. };
  159. };
  160. /* The MCP3021 supports standard and fast modes */
  161. mikrobus_adc: mcp3021@4c {
  162. compatible = "microchip,mcp3021";
  163. reg = <0x4c>;
  164. };
  165. eeprom@52 {
  166. compatible = "atmel,24c02";
  167. reg = <0x52>;
  168. pagesize = <16>;
  169. };
  170. };
  171. &i2c1 {
  172. /*
  173. * Routed to SFP, mikrobus, and PCIe.
  174. * SFP limits this to 100kHz, and requires an AT24C01A/02/04 with
  175. * address pins tied low, which takes addresses 0x50 and 0x51.
  176. * Mikrobus doesn't specify beyond an I2C bus being present.
  177. * PCIe uses ARP to assign addresses, or 0x63-0x64.
  178. */
  179. clock-frequency = <100000>;
  180. pinctrl-0 = <&clearfog_i2c1_pins>;
  181. pinctrl-names = "default";
  182. status = "okay";
  183. };
  184. &pinctrl {
  185. clearfog_i2c1_pins: i2c1-pins {
  186. /* SFP, PCIe, mSATA, mikrobus */
  187. marvell,pins = "mpp26", "mpp27";
  188. marvell,function = "i2c1";
  189. };
  190. clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins {
  191. marvell,pins = "mpp20";
  192. marvell,function = "gpio";
  193. };
  194. mikro_pins: mikro-pins {
  195. /* int: mpp22 rst: mpp29 */
  196. marvell,pins = "mpp22", "mpp29";
  197. marvell,function = "gpio";
  198. };
  199. mikro_spi_pins: mikro-spi-pins {
  200. marvell,pins = "mpp43";
  201. marvell,function = "spi1";
  202. };
  203. mikro_uart_pins: mikro-uart-pins {
  204. marvell,pins = "mpp24", "mpp25";
  205. marvell,function = "ua1";
  206. };
  207. };
  208. &spi1 {
  209. /*
  210. * Add SPI CS pins for clearfog:
  211. * CS0: W25Q32
  212. * CS1: PIC microcontroller (Pro models)
  213. * CS2: mikrobus
  214. */
  215. pinctrl-0 = <&spi1_pins &mikro_spi_pins>;
  216. pinctrl-names = "default";
  217. status = "okay";
  218. };
  219. &uart1 {
  220. /* mikrobus uart */
  221. pinctrl-0 = <&mikro_uart_pins>;
  222. pinctrl-names = "default";
  223. status = "okay";
  224. };