armada-385-db-88f6820-amc.dts 2.3 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /*
  3. * Device Tree file for Marvell Armada 385 AMC board
  4. * (DB-88F6820-AMC)
  5. *
  6. * Copyright (C) 2017 Allied Telesis Labs
  7. */
  8. /dts-v1/;
  9. #include "armada-385.dtsi"
  10. #include <dt-bindings/gpio/gpio.h>
  11. / {
  12. model = "Marvell Armada 385 AMC";
  13. compatible = "marvell,a385-db-amc", "marvell,armada385", "marvell,armada380";
  14. chosen {
  15. stdout-path = "serial0:115200n8";
  16. };
  17. aliases {
  18. ethernet0 = &eth0;
  19. ethernet1 = &eth1;
  20. spi1 = &spi1;
  21. };
  22. memory {
  23. device_type = "memory";
  24. reg = <0x00000000 0x80000000>; /* 2GB */
  25. };
  26. soc {
  27. ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
  28. MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
  29. };
  30. };
  31. &i2c0 {
  32. pinctrl-names = "default";
  33. pinctrl-0 = <&i2c0_pins>;
  34. status = "okay";
  35. };
  36. &uart0 {
  37. /*
  38. * Exported on the micro USB connector CON3
  39. * through an FTDI
  40. */
  41. pinctrl-names = "default";
  42. pinctrl-0 = <&uart0_pins>;
  43. status = "okay";
  44. };
  45. &eth0 {
  46. pinctrl-names = "default";
  47. /*
  48. * The Reference Clock 0 is used to provide a
  49. * clock to the PHY
  50. */
  51. pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
  52. status = "okay";
  53. phy = <&phy0>;
  54. phy-mode = "rgmii-id";
  55. };
  56. &eth2 {
  57. status = "okay";
  58. phy = <&phy1>;
  59. phy-mode = "sgmii";
  60. };
  61. &usb0 {
  62. status = "okay";
  63. };
  64. &mdio {
  65. pinctrl-names = "default";
  66. pinctrl-0 = <&mdio_pins>;
  67. phy0: ethernet-phy@1 {
  68. reg = <1>;
  69. };
  70. phy1: ethernet-phy@0 {
  71. reg = <0>;
  72. };
  73. };
  74. &nand_controller {
  75. status = "okay";
  76. nand@0 {
  77. reg = <0>;
  78. label = "pxa3xx_nand-0";
  79. nand-rb = <0>;
  80. nand-on-flash-bbt;
  81. partitions {
  82. compatible = "fixed-partitions";
  83. #address-cells = <1>;
  84. #size-cells = <1>;
  85. partition@0 {
  86. reg = <0x00000000 0x40000000>;
  87. label = "user";
  88. };
  89. };
  90. };
  91. };
  92. &pciec {
  93. status = "okay";
  94. };
  95. &pcie1 {
  96. /* Port 0, Lane 0 */
  97. status = "okay";
  98. };
  99. &spi1 {
  100. pinctrl-names = "default";
  101. pinctrl-0 = <&spi1_pins>;
  102. status = "okay";
  103. flash@0 {
  104. #address-cells = <1>;
  105. #size-cells = <1>;
  106. compatible = "jedec,spi-nor";
  107. reg = <0>; /* Chip select 0 */
  108. spi-max-frequency = <50000000>;
  109. m25p,fast-read;
  110. partitions {
  111. compatible = "fixed-partitions";
  112. #address-cells = <1>;
  113. #size-cells = <1>;
  114. partition@0 {
  115. reg = <0x00000000 0x00100000>;
  116. label = "u-boot";
  117. };
  118. partition@100000 {
  119. reg = <0x00100000 0x00040000>;
  120. label = "u-boot-env";
  121. };
  122. };
  123. };
  124. };
  125. &refclk {
  126. clock-frequency = <20000000>;
  127. };