armada-385-clearfog-gtr-s4.dts 1.2 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. #include "armada-385-clearfog-gtr.dtsi"
  3. / {
  4. model = "SolidRun Clearfog GTR S4";
  5. };
  6. &sfp0 {
  7. tx-fault-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>;
  8. };
  9. &mdio {
  10. switch0: switch0@4 {
  11. compatible = "marvell,mv88e6085";
  12. reg = <4>;
  13. pinctrl-names = "default";
  14. pinctrl-0 = <&cf_gtr_switch_reset_pins>;
  15. reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
  16. ports {
  17. #address-cells = <1>;
  18. #size-cells = <0>;
  19. port@1 {
  20. reg = <1>;
  21. label = "lan2";
  22. phy-handle = <&switch0phy0>;
  23. };
  24. port@2 {
  25. reg = <2>;
  26. label = "lan1";
  27. phy-handle = <&switch0phy1>;
  28. };
  29. port@3 {
  30. reg = <3>;
  31. label = "lan4";
  32. phy-handle = <&switch0phy2>;
  33. };
  34. port@4 {
  35. reg = <4>;
  36. label = "lan3";
  37. phy-handle = <&switch0phy3>;
  38. };
  39. port@5 {
  40. reg = <5>;
  41. label = "cpu";
  42. ethernet = <&eth1>;
  43. };
  44. };
  45. mdio {
  46. #address-cells = <1>;
  47. #size-cells = <0>;
  48. switch0phy0: switch0phy0@11 {
  49. reg = <0x11>;
  50. };
  51. switch0phy1: switch0phy1@12 {
  52. reg = <0x12>;
  53. };
  54. switch0phy2: switch0phy2@13 {
  55. reg = <0x13>;
  56. };
  57. switch0phy3: switch0phy3@14 {
  58. reg = <0x14>;
  59. };
  60. };
  61. };
  62. };