armada-385-atl-x530.dts 4.1 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /*
  3. * Device Tree file for Armada 385 Allied Telesis x530/GS980MX Board.
  4. (x530/AT-GS980MX)
  5. *
  6. Copyright (C) 2020 Allied Telesis Labs
  7. */
  8. /dts-v1/;
  9. #include "armada-385.dtsi"
  10. #include <dt-bindings/gpio/gpio.h>
  11. / {
  12. model = "x530/AT-GS980MX";
  13. compatible = "alliedtelesis,gs980mx", "alliedtelesis,x530", "marvell,armada385", "marvell,armada380";
  14. chosen {
  15. stdout-path = "serial1:115200n8";
  16. };
  17. memory {
  18. device_type = "memory";
  19. reg = <0x00000000 0x40000000>; /* 1GB */
  20. };
  21. soc {
  22. ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
  23. MBUS_ID(0x01, 0x3d) 0 0xf4800000 0x80000
  24. MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
  25. internal-regs {
  26. i2c0: i2c@11000 {
  27. pinctrl-names = "default";
  28. pinctrl-0 = <&i2c0_pins>;
  29. status = "okay";
  30. };
  31. uart0: serial@12000 {
  32. pinctrl-names = "default";
  33. pinctrl-0 = <&uart0_pins>;
  34. status = "okay";
  35. };
  36. };
  37. };
  38. };
  39. &pciec {
  40. status = "okay";
  41. };
  42. &pcie1 {
  43. status = "okay";
  44. reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
  45. reset-delay-us = <400000>;
  46. };
  47. &pcie2 {
  48. status = "okay";
  49. };
  50. &devbus_cs1 {
  51. compatible = "marvell,mvebu-devbus";
  52. status = "okay";
  53. devbus,bus-width = <8>;
  54. devbus,turn-off-ps = <60000>;
  55. devbus,badr-skew-ps = <0>;
  56. devbus,acc-first-ps = <124000>;
  57. devbus,acc-next-ps = <248000>;
  58. devbus,rd-setup-ps = <0>;
  59. devbus,rd-hold-ps = <0>;
  60. /* Write parameters */
  61. devbus,sync-enable = <0>;
  62. devbus,wr-high-ps = <60000>;
  63. devbus,wr-low-ps = <60000>;
  64. devbus,ale-wr-ps = <60000>;
  65. nvs@0 {
  66. status = "okay";
  67. compatible = "mtd-ram";
  68. reg = <0 0x00080000>;
  69. bank-width = <1>;
  70. label = "nvs";
  71. };
  72. };
  73. &pinctrl {
  74. i2c0_gpio_pins: i2c-gpio-pins-0 {
  75. marvell,pins = "mpp2", "mpp3";
  76. marvell,function = "gpio";
  77. };
  78. };
  79. &i2c0 {
  80. clock-frequency = <100000>;
  81. status = "okay";
  82. pinctrl-names = "default", "gpio";
  83. pinctrl-0 = <&i2c0_pins>;
  84. pinctrl-1 = <&i2c0_gpio_pins>;
  85. scl-gpio = <&gpio0 2 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
  86. sda-gpio = <&gpio0 3 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
  87. i2c0mux: mux@71 {
  88. #address-cells = <1>;
  89. #size-cells = <0>;
  90. compatible = "nxp,pca9544";
  91. reg = <0x71>;
  92. i2c-mux-idle-disconnect;
  93. i2c@0 { /* POE devices MUX */
  94. #address-cells = <1>;
  95. #size-cells = <0>;
  96. reg = <0>;
  97. };
  98. i2c@1 {
  99. #address-cells = <1>;
  100. #size-cells = <0>;
  101. reg = <1>;
  102. adt7476_2e: hwmon@2e {
  103. compatible = "adi,adt7476";
  104. reg = <0x2e>;
  105. };
  106. adt7476_2d: hwmon@2d {
  107. compatible = "adi,adt7476";
  108. reg = <0x2d>;
  109. };
  110. };
  111. i2c@2 {
  112. #address-cells = <1>;
  113. #size-cells = <0>;
  114. reg = <2>;
  115. rtc@68 {
  116. compatible = "dallas,ds1340";
  117. reg = <0x68>;
  118. };
  119. };
  120. i2c@3 {
  121. #address-cells = <1>;
  122. #size-cells = <0>;
  123. reg = <3>;
  124. gpio@20 {
  125. compatible = "nxp,pca9554";
  126. gpio-controller;
  127. #gpio-cells = <2>;
  128. reg = <0x20>;
  129. };
  130. };
  131. };
  132. };
  133. &usb0 {
  134. status = "okay";
  135. };
  136. &spi1 {
  137. pinctrl-names = "default";
  138. pinctrl-0 = <&spi1_pins>;
  139. status = "okay";
  140. flash@1 {
  141. #address-cells = <1>;
  142. #size-cells = <1>;
  143. compatible = "jedec,spi-nor";
  144. reg = <1>; /* Chip select 1 */
  145. spi-max-frequency = <54000000>;
  146. partitions {
  147. compatible = "fixed-partitions";
  148. #address-cells = <1>;
  149. #size-cells = <1>;
  150. partition@u-boot {
  151. reg = <0x00000000 0x00100000>;
  152. label = "u-boot";
  153. };
  154. partition@u-boot-env {
  155. reg = <0x00100000 0x00040000>;
  156. label = "u-boot-env";
  157. };
  158. partition@unused {
  159. reg = <0x00140000 0x00e80000>;
  160. label = "unused";
  161. };
  162. partition@idprom {
  163. reg = <0x00fc0000 0x00040000>;
  164. label = "idprom";
  165. };
  166. };
  167. };
  168. };
  169. &nand_controller {
  170. status = "okay";
  171. nand@0 {
  172. reg = <0>;
  173. label = "pxa3xx_nand-0";
  174. nand-rb = <0>;
  175. nand-on-flash-bbt;
  176. nand-ecc-strength = <4>;
  177. nand-ecc-step-size = <512>;
  178. marvell,nand-enable-arbiter;
  179. partitions {
  180. compatible = "fixed-partitions";
  181. #address-cells = <1>;
  182. #size-cells = <1>;
  183. partition@user {
  184. reg = <0x00000000 0x0f000000>;
  185. label = "user";
  186. };
  187. partition@errlog {
  188. /* Maximum mtdoops size is 8MB, so set to that. */
  189. reg = <0x0f000000 0x00800000>;
  190. label = "errlog";
  191. };
  192. partition@nand-bbt {
  193. reg = <0x0f800000 0x00800000>;
  194. label = "nand-bbt";
  195. };
  196. };
  197. };
  198. };