armada-381-netgear-gs110emx.dts 4.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. /* Copyright (c) 2021, Marcel Ziswiler <[email protected]> */
  3. /dts-v1/;
  4. #include "armada-385.dtsi"
  5. #include <dt-bindings/gpio/gpio.h>
  6. #include <dt-bindings/input/input.h>
  7. / {
  8. model = "Netgear GS110EMX";
  9. compatible = "netgear,gs110emx", "marvell,armada380";
  10. aliases {
  11. /* So that mvebu u-boot can update the MAC addresses */
  12. ethernet1 = &eth0;
  13. };
  14. chosen {
  15. stdout-path = "serial0:115200n8";
  16. };
  17. gpio-keys {
  18. compatible = "gpio-keys";
  19. pinctrl-0 = <&front_button_pins>;
  20. pinctrl-names = "default";
  21. key-factory-default {
  22. label = "Factory Default";
  23. gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
  24. linux,code = <KEY_RESTART>;
  25. };
  26. };
  27. memory {
  28. device_type = "memory";
  29. reg = <0x00000000 0x08000000>; /* 128 MB */
  30. };
  31. soc {
  32. ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
  33. MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
  34. MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
  35. MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
  36. MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
  37. internal-regs {
  38. rtc@a3800 {
  39. /*
  40. * If the rtc doesn't work, run "date reset"
  41. * twice in u-boot.
  42. */
  43. status = "okay";
  44. };
  45. };
  46. };
  47. };
  48. &eth0 {
  49. /* ethernet@70000 */
  50. bm,pool-long = <0>;
  51. bm,pool-short = <1>;
  52. buffer-manager = <&bm>;
  53. phy-mode = "rgmii-id";
  54. pinctrl-0 = <&ge0_rgmii_pins>;
  55. pinctrl-names = "default";
  56. status = "okay";
  57. fixed-link {
  58. full-duplex;
  59. pause;
  60. speed = <1000>;
  61. };
  62. };
  63. &mdio {
  64. pinctrl-names = "default";
  65. pinctrl-0 = <&mdio_pins>;
  66. status = "okay";
  67. switch@0 {
  68. compatible = "marvell,mv88e6190";
  69. #address-cells = <1>;
  70. #interrupt-cells = <2>;
  71. interrupt-controller;
  72. interrupt-parent = <&gpio1>;
  73. interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
  74. pinctrl-0 = <&switch_interrupt_pins>;
  75. pinctrl-names = "default";
  76. #size-cells = <0>;
  77. reg = <0>;
  78. mdio {
  79. #address-cells = <1>;
  80. #size-cells = <0>;
  81. switch0phy1: switch0phy1@1 {
  82. reg = <0x1>;
  83. };
  84. switch0phy2: switch0phy2@2 {
  85. reg = <0x2>;
  86. };
  87. switch0phy3: switch0phy3@3 {
  88. reg = <0x3>;
  89. };
  90. switch0phy4: switch0phy4@4 {
  91. reg = <0x4>;
  92. };
  93. switch0phy5: switch0phy5@5 {
  94. reg = <0x5>;
  95. };
  96. switch0phy6: switch0phy6@6 {
  97. reg = <0x6>;
  98. };
  99. switch0phy7: switch0phy7@7 {
  100. reg = <0x7>;
  101. };
  102. switch0phy8: switch0phy8@8 {
  103. reg = <0x8>;
  104. };
  105. };
  106. mdio-external {
  107. compatible = "marvell,mv88e6xxx-mdio-external";
  108. #address-cells = <1>;
  109. #size-cells = <0>;
  110. phy1: ethernet-phy@b {
  111. reg = <0xb>;
  112. compatible = "ethernet-phy-ieee802.3-c45";
  113. };
  114. phy2: ethernet-phy@c {
  115. reg = <0xc>;
  116. compatible = "ethernet-phy-ieee802.3-c45";
  117. };
  118. };
  119. ports {
  120. #address-cells = <1>;
  121. #size-cells = <0>;
  122. port@0 {
  123. ethernet = <&eth0>;
  124. label = "cpu";
  125. reg = <0>;
  126. fixed-link {
  127. full-duplex;
  128. pause;
  129. speed = <1000>;
  130. };
  131. };
  132. port@1 {
  133. label = "lan1";
  134. phy-handle = <&switch0phy1>;
  135. reg = <1>;
  136. };
  137. port@2 {
  138. label = "lan2";
  139. phy-handle = <&switch0phy2>;
  140. reg = <2>;
  141. };
  142. port@3 {
  143. label = "lan3";
  144. phy-handle = <&switch0phy3>;
  145. reg = <3>;
  146. };
  147. port@4 {
  148. label = "lan4";
  149. phy-handle = <&switch0phy4>;
  150. reg = <4>;
  151. };
  152. port@5 {
  153. label = "lan5";
  154. phy-handle = <&switch0phy5>;
  155. reg = <5>;
  156. };
  157. port@6 {
  158. label = "lan6";
  159. phy-handle = <&switch0phy6>;
  160. reg = <6>;
  161. };
  162. port@7 {
  163. label = "lan7";
  164. phy-handle = <&switch0phy7>;
  165. reg = <7>;
  166. };
  167. port@8 {
  168. label = "lan8";
  169. phy-handle = <&switch0phy8>;
  170. reg = <8>;
  171. };
  172. port@9 {
  173. /* 88X3310P external phy */
  174. label = "lan9";
  175. phy-handle = <&phy1>;
  176. phy-mode = "xaui";
  177. reg = <9>;
  178. };
  179. port@a {
  180. /* 88X3310P external phy */
  181. label = "lan10";
  182. phy-handle = <&phy2>;
  183. phy-mode = "xaui";
  184. reg = <0xa>;
  185. };
  186. };
  187. };
  188. };
  189. &pinctrl {
  190. front_button_pins: front-button-pins {
  191. marvell,pins = "mpp38";
  192. marvell,function = "gpio";
  193. };
  194. switch_interrupt_pins: switch-interrupt-pins {
  195. marvell,pins = "mpp39";
  196. marvell,function = "gpio";
  197. };
  198. };
  199. &spi0 {
  200. pinctrl-0 = <&spi0_pins>;
  201. pinctrl-names = "default";
  202. status = "okay";
  203. flash@0 {
  204. #address-cells = <1>;
  205. #size-cells = <1>;
  206. compatible = "jedec,spi-nor";
  207. reg = <0>; /* Chip select 0 */
  208. spi-max-frequency = <3000000>;
  209. partitions {
  210. compatible = "fixed-partitions";
  211. #address-cells = <1>;
  212. #size-cells = <1>;
  213. partition@0 {
  214. label = "boot";
  215. read-only;
  216. reg = <0x00000000 0x00100000>;
  217. };
  218. partition@100000 {
  219. label = "env";
  220. reg = <0x00100000 0x00010000>;
  221. };
  222. partition@200000 {
  223. label = "rsv";
  224. reg = <0x00110000 0x00010000>;
  225. };
  226. partition@300000 {
  227. label = "image0";
  228. reg = <0x00120000 0x00900000>;
  229. };
  230. partition@400000 {
  231. label = "config";
  232. reg = <0x00a20000 0x00300000>;
  233. };
  234. partition@480000 {
  235. label = "debug";
  236. reg = <0x00d20000 0x002e0000>;
  237. };
  238. };
  239. };
  240. };
  241. &uart0 {
  242. pinctrl-0 = <&uart0_pins>;
  243. pinctrl-names = "default";
  244. status = "okay";
  245. };