armada-375-db.dts 2.9 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Device Tree file for Marvell Armada 375 evaluation board
  4. * (DB-88F6720)
  5. *
  6. * Copyright (C) 2014 Marvell
  7. *
  8. * Gregory CLEMENT <[email protected]>
  9. * Thomas Petazzoni <[email protected]>
  10. */
  11. /dts-v1/;
  12. #include <dt-bindings/gpio/gpio.h>
  13. #include "armada-375.dtsi"
  14. / {
  15. model = "Marvell Armada 375 Development Board";
  16. compatible = "marvell,a375-db", "marvell,armada375";
  17. chosen {
  18. stdout-path = "serial0:115200n8";
  19. };
  20. memory@0 {
  21. device_type = "memory";
  22. reg = <0x00000000 0x40000000>; /* 1 GB */
  23. };
  24. soc {
  25. ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
  26. MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
  27. MBUS_ID(0x09, 0x09) 0 0xf1100000 0x10000
  28. MBUS_ID(0x09, 0x05) 0 0xf1110000 0x10000>;
  29. };
  30. };
  31. &pciec {
  32. status = "okay";
  33. };
  34. /*
  35. * The two PCIe units are accessible through
  36. * standard PCIe slots on the board.
  37. */
  38. &pcie0 {
  39. /* Port 0, Lane 0 */
  40. status = "okay";
  41. };
  42. &pcie1 {
  43. /* Port 1, Lane 0 */
  44. status = "okay";
  45. };
  46. &spi0 {
  47. pinctrl-0 = <&spi0_pins>;
  48. pinctrl-names = "default";
  49. /*
  50. * SPI conflicts with NAND, so we disable it here, and
  51. * select NAND as the enabled device by default.
  52. */
  53. status = "disabled";
  54. flash@0 {
  55. #address-cells = <1>;
  56. #size-cells = <1>;
  57. compatible = "n25q128a13", "jedec,spi-nor";
  58. reg = <0>; /* Chip select 0 */
  59. spi-max-frequency = <108000000>;
  60. };
  61. };
  62. &i2c0 {
  63. status = "okay";
  64. clock-frequency = <100000>;
  65. pinctrl-0 = <&i2c0_pins>;
  66. pinctrl-names = "default";
  67. };
  68. &i2c1 {
  69. status = "okay";
  70. clock-frequency = <100000>;
  71. pinctrl-0 = <&i2c1_pins>;
  72. pinctrl-names = "default";
  73. };
  74. &uart0 {
  75. status = "okay";
  76. };
  77. &pinctrl {
  78. sdio_st_pins: sdio-st-pins {
  79. marvell,pins = "mpp44", "mpp45";
  80. marvell,function = "gpio";
  81. };
  82. };
  83. &sata {
  84. status = "okay";
  85. nr-ports = <2>;
  86. };
  87. &nand_controller {
  88. status = "okay";
  89. pinctrl-0 = <&nand_pins>;
  90. pinctrl-names = "default";
  91. nand@0 {
  92. reg = <0>;
  93. label = "pxa3xx_nand-0";
  94. nand-rb = <0>;
  95. marvell,nand-keep-config;
  96. nand-on-flash-bbt;
  97. nand-ecc-strength = <4>;
  98. nand-ecc-step-size = <512>;
  99. partitions {
  100. compatible = "fixed-partitions";
  101. #address-cells = <1>;
  102. #size-cells = <1>;
  103. partition@0 {
  104. label = "U-Boot";
  105. reg = <0 0x800000>;
  106. };
  107. partition@800000 {
  108. label = "Linux";
  109. reg = <0x800000 0x800000>;
  110. };
  111. partition@1000000 {
  112. label = "Filesystem";
  113. reg = <0x1000000 0x3f000000>;
  114. };
  115. };
  116. };
  117. };
  118. &usb1 {
  119. status = "okay";
  120. };
  121. &usb2 {
  122. status = "okay";
  123. };
  124. &sdio {
  125. pinctrl-0 = <&sdio_pins &sdio_st_pins>;
  126. pinctrl-names = "default";
  127. status = "okay";
  128. cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
  129. wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
  130. };
  131. &mdio {
  132. phy0: ethernet-phy@0 {
  133. reg = <0>;
  134. };
  135. phy3: ethernet-phy@3 {
  136. reg = <3>;
  137. };
  138. };
  139. &ethernet {
  140. status = "okay";
  141. };
  142. &eth0 {
  143. status = "okay";
  144. phy = <&phy0>;
  145. phy-mode = "rgmii-id";
  146. };
  147. &eth1 {
  148. status = "okay";
  149. phy = <&phy3>;
  150. phy-mode = "gmii";
  151. };