armada-370-rd.dts 4.7 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Device Tree file for Marvell Armada 370 Reference Design board
  4. * (RD-88F6710-A1)
  5. *
  6. * Copied from arch/arm/boot/dts/armada-370-db.dts
  7. *
  8. * Copyright (C) 2013 Florian Fainelli <[email protected]>
  9. *
  10. * Note: this Device Tree assumes that the bootloader has remapped the
  11. * internal registers to 0xf1000000 (instead of the default
  12. * 0xd0000000). The 0xf1000000 is the default used by the recent,
  13. * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
  14. * boards were delivered with an older version of the bootloader that
  15. * left internal registers mapped at 0xd0000000. If you are in this
  16. * situation, you should either update your bootloader (preferred
  17. * solution) or the below Device Tree should be adjusted.
  18. */
  19. /dts-v1/;
  20. #include <dt-bindings/input/input.h>
  21. #include <dt-bindings/interrupt-controller/irq.h>
  22. #include <dt-bindings/gpio/gpio.h>
  23. #include "armada-370.dtsi"
  24. / {
  25. model = "Marvell Armada 370 Reference Design";
  26. compatible = "marvell,a370-rd", "marvell,armada370", "marvell,armada-370-xp";
  27. chosen {
  28. stdout-path = "serial0:115200n8";
  29. };
  30. memory@0 {
  31. device_type = "memory";
  32. reg = <0x00000000 0x20000000>; /* 512 MB */
  33. };
  34. soc {
  35. ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
  36. MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
  37. MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
  38. internal-regs {
  39. serial@12000 {
  40. status = "okay";
  41. };
  42. sata@a0000 {
  43. nr-ports = <2>;
  44. status = "okay";
  45. };
  46. ethernet@70000 {
  47. status = "okay";
  48. phy = <&phy0>;
  49. phy-mode = "sgmii";
  50. };
  51. ethernet@74000 {
  52. pinctrl-0 = <&ge1_rgmii_pins>;
  53. pinctrl-names = "default";
  54. status = "okay";
  55. phy-mode = "rgmii-id";
  56. fixed-link {
  57. speed = <1000>;
  58. full-duplex;
  59. };
  60. };
  61. mvsdio@d4000 {
  62. pinctrl-0 = <&sdio_pins1>;
  63. pinctrl-names = "default";
  64. status = "okay";
  65. /* No CD or WP GPIOs */
  66. broken-cd;
  67. };
  68. usb@50000 {
  69. status = "okay";
  70. };
  71. usb@51000 {
  72. status = "okay";
  73. };
  74. gpio-keys {
  75. compatible = "gpio-keys";
  76. button {
  77. label = "Software Button";
  78. linux,code = <KEY_POWER>;
  79. gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
  80. };
  81. };
  82. gpio-fan {
  83. compatible = "gpio-fan";
  84. gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
  85. gpio-fan,speed-map = <0 0 3000 1>;
  86. pinctrl-0 = <&fan_pins>;
  87. pinctrl-names = "default";
  88. };
  89. gpio_leds {
  90. compatible = "gpio-leds";
  91. pinctrl-names = "default";
  92. pinctrl-0 = <&led_pins>;
  93. sw_led {
  94. label = "370rd:green:sw";
  95. gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
  96. default-state = "keep";
  97. };
  98. };
  99. };
  100. };
  101. };
  102. &pciec {
  103. status = "okay";
  104. /* Internal mini-PCIe connector */
  105. pcie@1,0 {
  106. /* Port 0, Lane 0 */
  107. status = "okay";
  108. };
  109. /* Internal mini-PCIe connector */
  110. pcie@2,0 {
  111. /* Port 1, Lane 0 */
  112. status = "okay";
  113. };
  114. };
  115. &mdio {
  116. pinctrl-0 = <&mdio_pins>;
  117. pinctrl-names = "default";
  118. phy0: ethernet-phy@0 {
  119. reg = <0>;
  120. };
  121. switch: switch@10 {
  122. compatible = "marvell,mv88e6085";
  123. #address-cells = <1>;
  124. #size-cells = <0>;
  125. reg = <0x10>;
  126. interrupt-controller;
  127. #interrupt-cells = <2>;
  128. ports {
  129. #address-cells = <1>;
  130. #size-cells = <0>;
  131. port@0 {
  132. reg = <0>;
  133. label = "lan0";
  134. };
  135. port@1 {
  136. reg = <1>;
  137. label = "lan1";
  138. };
  139. port@2 {
  140. reg = <2>;
  141. label = "lan2";
  142. };
  143. port@3 {
  144. reg = <3>;
  145. label = "lan3";
  146. };
  147. port@5 {
  148. reg = <5>;
  149. label = "cpu";
  150. ethernet = <&eth1>;
  151. fixed-link {
  152. speed = <1000>;
  153. full-duplex;
  154. };
  155. };
  156. };
  157. mdio {
  158. #address-cells = <1>;
  159. #size-cells = <0>;
  160. switchphy0: switchphy@0 {
  161. reg = <0>;
  162. interrupt-parent = <&switch>;
  163. interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
  164. };
  165. switchphy1: switchphy@1 {
  166. reg = <1>;
  167. interrupt-parent = <&switch>;
  168. interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
  169. };
  170. switchphy2: switchphy@2 {
  171. reg = <2>;
  172. interrupt-parent = <&switch>;
  173. interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
  174. };
  175. switchphy3: switchphy@3 {
  176. reg = <3>;
  177. interrupt-parent = <&switch>;
  178. interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
  179. };
  180. };
  181. };
  182. };
  183. &pinctrl {
  184. fan_pins: fan-pins {
  185. marvell,pins = "mpp8";
  186. marvell,function = "gpio";
  187. };
  188. led_pins: led-pins {
  189. marvell,pins = "mpp32";
  190. marvell,function = "gpio";
  191. };
  192. };
  193. &nand_controller {
  194. status = "okay";
  195. nand@0 {
  196. reg = <0>;
  197. label = "pxa3xx_nand-0";
  198. nand-rb = <0>;
  199. marvell,nand-keep-config;
  200. nand-on-flash-bbt;
  201. partitions {
  202. compatible = "fixed-partitions";
  203. #address-cells = <1>;
  204. #size-cells = <1>;
  205. partition@0 {
  206. label = "U-Boot";
  207. reg = <0 0x800000>;
  208. };
  209. partition@800000 {
  210. label = "Linux";
  211. reg = <0x800000 0x800000>;
  212. };
  213. partition@1000000 {
  214. label = "Filesystem";
  215. reg = <0x1000000 0x3f000000>;
  216. };
  217. };
  218. };
  219. };