arm-realview-eb-a9mp.dts 1.9 KB

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  1. /*
  2. * Copyright 2016 Linaro Ltd
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a copy
  5. * of this software and associated documentation files (the "Software"), to deal
  6. * in the Software without restriction, including without limitation the rights
  7. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  8. * copies of the Software, and to permit persons to whom the Software is
  9. * furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  19. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  20. * THE SOFTWARE.
  21. */
  22. /dts-v1/;
  23. #include "arm-realview-eb-mp.dtsi"
  24. / {
  25. model = "ARM RealView EB Cortex A9 MPCore";
  26. /*
  27. * This is the Cortex A9 MPCore tile used with the
  28. * RealView EB.
  29. */
  30. cpus {
  31. #address-cells = <1>;
  32. #size-cells = <0>;
  33. enable-method = "arm,realview-smp";
  34. A9_0: cpu@0 {
  35. device_type = "cpu";
  36. compatible = "arm,cortex-a9";
  37. reg = <0>;
  38. next-level-cache = <&L2>;
  39. };
  40. A9_1: cpu@1 {
  41. device_type = "cpu";
  42. compatible = "arm,cortex-a9";
  43. reg = <1>;
  44. next-level-cache = <&L2>;
  45. };
  46. A9_2: cpu@2 {
  47. device_type = "cpu";
  48. compatible = "arm,cortex-a9";
  49. reg = <2>;
  50. next-level-cache = <&L2>;
  51. };
  52. A9_3: cpu@3 {
  53. device_type = "cpu";
  54. compatible = "arm,cortex-a9";
  55. reg = <3>;
  56. next-level-cache = <&L2>;
  57. };
  58. };
  59. };
  60. &pmu {
  61. interrupt-affinity = <&A9_0>, <&A9_1>, <&A9_2>, <&A9_3>;
  62. };