am57xx-cl-som-am57x.dts 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Support for CompuLab CL-SOM-AM57x System-on-Module
  4. *
  5. * Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/
  6. * Author: Dmitry Lifshitz <[email protected]>
  7. */
  8. /dts-v1/;
  9. #include <dt-bindings/gpio/gpio.h>
  10. #include <dt-bindings/interrupt-controller/irq.h>
  11. #include "am5728.dtsi"
  12. / {
  13. model = "CompuLab CL-SOM-AM57x";
  14. compatible = "compulab,cl-som-am57x", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7";
  15. memory@0 {
  16. device_type = "memory";
  17. reg = <0x0 0x80000000 0x0 0x20000000>; /* 512 MB - minimal configuration */
  18. };
  19. leds {
  20. compatible = "gpio-leds";
  21. pinctrl-names = "default";
  22. pinctrl-0 = <&leds_pins_default>;
  23. led0 {
  24. label = "cl-som-am57x:green";
  25. gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;
  26. linux,default-trigger = "heartbeat";
  27. default-state = "off";
  28. };
  29. };
  30. vdd_3v3: fixedregulator-vdd_3v3 {
  31. compatible = "regulator-fixed";
  32. regulator-name = "vdd_3v3";
  33. regulator-min-microvolt = <3300000>;
  34. regulator-max-microvolt = <3300000>;
  35. };
  36. ads7846reg: fixedregulator-ads7846-reg {
  37. compatible = "regulator-fixed";
  38. regulator-name = "ads7846-reg";
  39. regulator-min-microvolt = <3300000>;
  40. regulator-max-microvolt = <3300000>;
  41. };
  42. sound0: sound0 {
  43. compatible = "simple-audio-card";
  44. simple-audio-card,name = "CL-SOM-AM57x-Sound-Card";
  45. simple-audio-card,format = "i2s";
  46. simple-audio-card,bitclock-master = <&dailink0_master>;
  47. simple-audio-card,frame-master = <&dailink0_master>;
  48. simple-audio-card,widgets =
  49. "Headphone", "Headphone Jack",
  50. "Microphone", "Microphone Jack",
  51. "Line", "Line Jack";
  52. simple-audio-card,routing =
  53. "Headphone Jack", "RHPOUT",
  54. "Headphone Jack", "LHPOUT",
  55. "LLINEIN", "Line Jack",
  56. "MICIN", "Mic Bias",
  57. "Mic Bias", "Microphone Jack";
  58. dailink0_master: simple-audio-card,cpu {
  59. sound-dai = <&mcasp3>;
  60. };
  61. simple-audio-card,codec {
  62. sound-dai = <&wm8731>;
  63. system-clock-frequency = <12000000>;
  64. };
  65. };
  66. };
  67. &dra7_pmx_core {
  68. leds_pins_default: leds_pins_default {
  69. pinctrl-single,pins = <
  70. DRA7XX_CORE_IOPAD(0x347c, PIN_OUTPUT | MUX_MODE14) /* gpmc_a15.gpio2_5 */
  71. >;
  72. };
  73. i2c1_pins_default: i2c1_pins_default {
  74. pinctrl-single,pins = <
  75. DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda.sda */
  76. DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl.scl */
  77. >;
  78. };
  79. i2c3_pins_default: i2c3_pins_default {
  80. pinctrl-single,pins = <
  81. DRA7XX_CORE_IOPAD(0x36a4, PIN_INPUT| MUX_MODE10) /* mcasp1_aclkx.i2c3_sda */
  82. DRA7XX_CORE_IOPAD(0x36a8, PIN_INPUT| MUX_MODE10) /* mcasp1_fsx.i2c3_scl */
  83. >;
  84. };
  85. i2c4_pins_default: i2c4_pins_default {
  86. pinctrl-single,pins = <
  87. DRA7XX_CORE_IOPAD(0x36ac, PIN_INPUT| MUX_MODE10) /* mcasp1_acl.i2c4_sda */
  88. DRA7XX_CORE_IOPAD(0x36b0, PIN_INPUT| MUX_MODE10) /* mcasp1_fsr.i2c4_scl */
  89. >;
  90. };
  91. tps659038_pins_default: tps659038_pins_default {
  92. pinctrl-single,pins = <
  93. DRA7XX_CORE_IOPAD(0x3818, PIN_INPUT_PULLUP | MUX_MODE14) /* wakeup0.gpio1_0 */
  94. >;
  95. };
  96. mmc2_pins_default: mmc2_pins_default {
  97. pinctrl-single,pins = <
  98. DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
  99. DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
  100. DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
  101. DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
  102. DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
  103. DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
  104. DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
  105. DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
  106. DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
  107. DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
  108. >;
  109. };
  110. qspi1_pins: pinmux_qspi1_pins {
  111. pinctrl-single,pins = <
  112. DRA7XX_CORE_IOPAD(0x3474, PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
  113. DRA7XX_CORE_IOPAD(0x3480, PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d0 */
  114. DRA7XX_CORE_IOPAD(0x3484, PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d1 */
  115. DRA7XX_CORE_IOPAD(0x3488, PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
  116. DRA7XX_CORE_IOPAD(0x34b8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
  117. DRA7XX_CORE_IOPAD(0x34bc, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */
  118. >;
  119. };
  120. cpsw_pins_default: cpsw_pins_default {
  121. pinctrl-single,pins = <
  122. /* Slave at addr 0x0 */
  123. DRA7XX_CORE_IOPAD(0x3650, PIN_OUTPUT | MUX_MODE0) /* rgmii0_tclk */
  124. DRA7XX_CORE_IOPAD(0x3654, PIN_OUTPUT | MUX_MODE0) /* rgmii0_tctl */
  125. DRA7XX_CORE_IOPAD(0x3658, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3 */
  126. DRA7XX_CORE_IOPAD(0x365c, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td2 */
  127. DRA7XX_CORE_IOPAD(0x3660, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td1 */
  128. DRA7XX_CORE_IOPAD(0x3664, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td0 */
  129. DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rclk */
  130. DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rctl */
  131. DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rd3 */
  132. DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rd2 */
  133. DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rd1 */
  134. DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rd0 */
  135. /* Slave at addr 0x1 */
  136. DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_tclk */
  137. DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
  138. DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
  139. DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
  140. DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
  141. DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
  142. DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
  143. DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
  144. DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
  145. DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
  146. DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
  147. DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
  148. >;
  149. };
  150. cpsw_pins_sleep: cpsw_pins_sleep {
  151. pinctrl-single,pins = <
  152. /* Slave 1 */
  153. DRA7XX_CORE_IOPAD(0x3650, PIN_INPUT | MUX_MODE15)
  154. DRA7XX_CORE_IOPAD(0x3654, PIN_INPUT | MUX_MODE15)
  155. DRA7XX_CORE_IOPAD(0x3658, PIN_INPUT | MUX_MODE15)
  156. DRA7XX_CORE_IOPAD(0x365c, PIN_INPUT | MUX_MODE15)
  157. DRA7XX_CORE_IOPAD(0x3660, PIN_INPUT | MUX_MODE15)
  158. DRA7XX_CORE_IOPAD(0x3664, PIN_INPUT | MUX_MODE15)
  159. DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT | MUX_MODE15)
  160. DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT | MUX_MODE15)
  161. DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT | MUX_MODE15)
  162. DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE15)
  163. DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE15)
  164. DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE15)
  165. /* Slave 2 */
  166. DRA7XX_CORE_IOPAD(0x3598, PIN_INPUT | MUX_MODE15)
  167. DRA7XX_CORE_IOPAD(0x359c, PIN_INPUT | MUX_MODE15)
  168. DRA7XX_CORE_IOPAD(0x35a0, PIN_INPUT | MUX_MODE15)
  169. DRA7XX_CORE_IOPAD(0x35a4, PIN_INPUT | MUX_MODE15)
  170. DRA7XX_CORE_IOPAD(0x35a8, PIN_INPUT | MUX_MODE15)
  171. DRA7XX_CORE_IOPAD(0x35ac, PIN_INPUT | MUX_MODE15)
  172. DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE15)
  173. DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE15)
  174. DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE15)
  175. DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE15)
  176. DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE15)
  177. DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE15)
  178. >;
  179. };
  180. davinci_mdio_pins_default: davinci_mdio_pins_default {
  181. pinctrl-single,pins = <
  182. /* MDIO */
  183. DRA7XX_CORE_IOPAD(0x3590, PIN_OUTPUT_PULLUP | MUX_MODE3)/* vin2a_d10.mdio_mclk */
  184. DRA7XX_CORE_IOPAD(0x3594, PIN_INPUT_PULLUP | MUX_MODE3) /* vin2a_d11.mdio_d */
  185. >;
  186. };
  187. davinci_mdio_pins_sleep: davinci_mdio_pins_sleep {
  188. pinctrl-single,pins = <
  189. DRA7XX_CORE_IOPAD(0x3590, PIN_INPUT | MUX_MODE15)
  190. DRA7XX_CORE_IOPAD(0x3594, PIN_INPUT | MUX_MODE15)
  191. >;
  192. };
  193. ads7846_pins: pinmux_ads7846_pins {
  194. pinctrl-single,pins = <
  195. DRA7XX_CORE_IOPAD(0x3464, PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpmc_a9.gpio1_31 */
  196. >;
  197. };
  198. mcasp3_pins_default: mcasp3_pins_default {
  199. pinctrl-single,pins = <
  200. DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx.mcasp3_aclkx */
  201. DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx.mcasp3_fsx */
  202. DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0.mcasp3_axr0 */
  203. DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1.mcasp3_axr1 */
  204. >;
  205. };
  206. mcasp3_pins_sleep: mcasp3_pins_sleep {
  207. pinctrl-single,pins = <
  208. DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT | MUX_MODE15)
  209. DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT | MUX_MODE15)
  210. DRA7XX_CORE_IOPAD(0x372c, PIN_INPUT | MUX_MODE15)
  211. DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT | MUX_MODE15)
  212. >;
  213. };
  214. };
  215. &i2c1 {
  216. status = "okay";
  217. pinctrl-names = "default";
  218. pinctrl-0 = <&i2c1_pins_default>;
  219. clock-frequency = <400000>;
  220. };
  221. &i2c3 {
  222. status = "okay";
  223. pinctrl-names = "default";
  224. pinctrl-0 = <&i2c3_pins_default>;
  225. clock-frequency = <400000>;
  226. };
  227. &i2c4 {
  228. status = "okay";
  229. pinctrl-names = "default";
  230. pinctrl-0 = <&i2c4_pins_default>;
  231. clock-frequency = <400000>;
  232. tps659038: tps659038@58 {
  233. compatible = "ti,tps659038";
  234. reg = <0x58>;
  235. interrupt-parent = <&gpio1>;
  236. interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
  237. pinctrl-names = "default";
  238. pinctrl-0 = <&tps659038_pins_default>;
  239. #interrupt-cells = <2>;
  240. interrupt-controller;
  241. ti,system-power-controller;
  242. tps659038_pmic {
  243. compatible = "ti,tps659038-pmic";
  244. regulators {
  245. smps12_reg: smps12 {
  246. /* VDD_MPU */
  247. regulator-name = "smps12";
  248. regulator-min-microvolt = < 850000>;
  249. regulator-max-microvolt = <1250000>;
  250. regulator-always-on;
  251. regulator-boot-on;
  252. };
  253. smps3_reg: smps3 {
  254. /* VDD_DDR */
  255. regulator-name = "smps3";
  256. regulator-min-microvolt = <1500000>;
  257. regulator-max-microvolt = <1500000>;
  258. regulator-always-on;
  259. regulator-boot-on;
  260. };
  261. smps45_reg: smps45 {
  262. /* VDD_DSPEVE */
  263. regulator-name = "smps45";
  264. regulator-min-microvolt = < 850000>;
  265. regulator-max-microvolt = <1250000>;
  266. regulator-always-on;
  267. regulator-boot-on;
  268. };
  269. smps6_reg: smps6 {
  270. /* VDD_GPU */
  271. regulator-name = "smps6";
  272. regulator-min-microvolt = < 850000>;
  273. regulator-max-microvolt = <1250000>;
  274. regulator-always-on;
  275. regulator-boot-on;
  276. };
  277. smps7_reg: smps7 {
  278. /* VDD_CORE */
  279. regulator-name = "smps7";
  280. regulator-min-microvolt = < 850000>;
  281. regulator-max-microvolt = <1160000>;
  282. regulator-always-on;
  283. regulator-boot-on;
  284. };
  285. smps8_reg: smps8 {
  286. /* VDD_IVA */
  287. regulator-name = "smps8";
  288. regulator-min-microvolt = < 850000>;
  289. regulator-max-microvolt = <1250000>;
  290. regulator-always-on;
  291. regulator-boot-on;
  292. };
  293. smps9_reg: smps9 {
  294. /* PMIC_3V3 */
  295. regulator-name = "smps9";
  296. regulator-min-microvolt = <3300000>;
  297. regulator-max-microvolt = <3300000>;
  298. regulator-always-on;
  299. regulator-boot-on;
  300. };
  301. ldo1_reg: ldo1 {
  302. /* VDD_SD / VDDSHV8 */
  303. regulator-name = "ldo1";
  304. regulator-min-microvolt = <1800000>;
  305. regulator-max-microvolt = <3300000>;
  306. regulator-boot-on;
  307. regulator-always-on;
  308. };
  309. ldo2_reg: ldo2 {
  310. /* VDD_1V8 */
  311. regulator-name = "ldo2";
  312. regulator-min-microvolt = <1800000>;
  313. regulator-max-microvolt = <1800000>;
  314. regulator-always-on;
  315. regulator-boot-on;
  316. };
  317. ldo3_reg: ldo3 {
  318. /* VDDA_1V8_PHYA - supplies VDDA_SATA, VDDA_USB1/2/3 */
  319. regulator-name = "ldo3";
  320. regulator-min-microvolt = <1800000>;
  321. regulator-max-microvolt = <1800000>;
  322. regulator-always-on;
  323. regulator-boot-on;
  324. };
  325. ldo4_reg: ldo4 {
  326. /* VDDA_1V8_PHYB - supplies VDDA_HDMI, VDDA_PCIE/0/1 */
  327. regulator-name = "ldo4";
  328. regulator-min-microvolt = <1800000>;
  329. regulator-max-microvolt = <1800000>;
  330. regulator-always-on;
  331. regulator-boot-on;
  332. };
  333. ldo9_reg: ldo9 {
  334. /* VDD_RTC */
  335. regulator-name = "ldo9";
  336. regulator-min-microvolt = <1050000>;
  337. regulator-max-microvolt = <1050000>;
  338. regulator-always-on;
  339. regulator-boot-on;
  340. };
  341. ldoln_reg: ldoln {
  342. /* VDDA_1V8_PLL */
  343. regulator-name = "ldoln";
  344. regulator-min-microvolt = <1800000>;
  345. regulator-max-microvolt = <1800000>;
  346. regulator-always-on;
  347. regulator-boot-on;
  348. };
  349. ldousb_reg: ldousb {
  350. /* VDDA_3V_USB: VDDA_USBHS33 */
  351. regulator-name = "ldousb";
  352. regulator-min-microvolt = <3300000>;
  353. regulator-max-microvolt = <3300000>;
  354. regulator-always-on;
  355. regulator-boot-on;
  356. };
  357. /* regen1 not used */
  358. };
  359. };
  360. tps659038_pwr_button: tps659038_pwr_button {
  361. compatible = "ti,palmas-pwrbutton";
  362. interrupt-parent = <&tps659038>;
  363. interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
  364. wakeup-source;
  365. ti,palmas-long-press-seconds = <12>;
  366. };
  367. tps659038_gpio: tps659038_gpio {
  368. compatible = "ti,palmas-gpio";
  369. gpio-controller;
  370. #gpio-cells = <2>;
  371. };
  372. };
  373. rtc0: rtc@56 {
  374. compatible = "emmicro,em3027";
  375. reg = <0x56>;
  376. };
  377. eeprom_module: atmel@50 {
  378. compatible = "atmel,24c08";
  379. reg = <0x50>;
  380. pagesize = <16>;
  381. };
  382. wm8731: wm8731@1a {
  383. #sound-dai-cells = <0>;
  384. compatible = "wlf,wm8731";
  385. reg = <0x1a>;
  386. status = "okay";
  387. };
  388. };
  389. &cpu0 {
  390. cpu0-supply = <&smps12_reg>;
  391. voltage-tolerance = <1>;
  392. };
  393. &sata {
  394. status = "okay";
  395. };
  396. &mailbox5 {
  397. status = "okay";
  398. mbox_ipu1_ipc3x: mbox-ipu1-ipc3x {
  399. status = "okay";
  400. };
  401. mbox_dsp1_ipc3x: mbox-dsp1-ipc3x {
  402. status = "okay";
  403. };
  404. };
  405. &mailbox6 {
  406. status = "okay";
  407. mbox_ipu2_ipc3x: mbox-ipu2-ipc3x {
  408. status = "okay";
  409. };
  410. mbox_dsp2_ipc3x: mbox-dsp2-ipc3x {
  411. status = "okay";
  412. };
  413. };
  414. &mmc2 {
  415. status = "okay";
  416. pinctrl-names = "default";
  417. pinctrl-0 = <&mmc2_pins_default>;
  418. vmmc-supply = <&vdd_3v3>;
  419. bus-width = <8>;
  420. ti,non-removable;
  421. cap-mmc-dual-data-rate;
  422. };
  423. &qspi {
  424. status = "okay";
  425. pinctrl-names = "default";
  426. pinctrl-0 = <&qspi1_pins>;
  427. spi-max-frequency = <48000000>;
  428. spi_flash: flash@0 {
  429. #address-cells = <1>;
  430. #size-cells = <1>;
  431. compatible = "spansion,m25p80", "jedec,spi-nor";
  432. reg = <0>; /* CS0 */
  433. spi-max-frequency = <48000000>;
  434. partition@0 {
  435. label = "uboot";
  436. reg = <0x0 0xc0000>;
  437. };
  438. partition@c0000 {
  439. label = "uboot environment";
  440. reg = <0xc0000 0x40000>;
  441. };
  442. partition@100000 {
  443. label = "reserved";
  444. reg = <0x100000 0x0>;
  445. };
  446. };
  447. /* touch controller */
  448. touchscreen@1 {
  449. pinctrl-names = "default";
  450. pinctrl-0 = <&ads7846_pins>;
  451. compatible = "ti,ads7846";
  452. vcc-supply = <&ads7846reg>;
  453. reg = <1>; /* CS1 */
  454. spi-max-frequency = <1500000>;
  455. interrupt-parent = <&gpio1>;
  456. interrupts = <31 0>;
  457. pendown-gpio = <&gpio1 31 GPIO_ACTIVE_LOW>;
  458. ti,x-min = /bits/ 16 <0x0>;
  459. ti,x-max = /bits/ 16 <0x0fff>;
  460. ti,y-min = /bits/ 16 <0x0>;
  461. ti,y-max = /bits/ 16 <0x0fff>;
  462. ti,x-plate-ohms = /bits/ 16 <180>;
  463. ti,pressure-max = /bits/ 16 <255>;
  464. ti,debounce-max = /bits/ 16 <30>;
  465. ti,debounce-tol = /bits/ 16 <10>;
  466. ti,debounce-rep = /bits/ 16 <1>;
  467. wakeup-source;
  468. };
  469. };
  470. &mac_sw {
  471. status = "okay";
  472. pinctrl-names = "default", "sleep";
  473. pinctrl-0 = <&cpsw_pins_default>;
  474. pinctrl-1 = <&cpsw_pins_sleep>;
  475. };
  476. &cpsw_port1 {
  477. phy-handle = <&ethphy0>;
  478. phy-mode = "rgmii-txid";
  479. ti,dual-emac-pvid = <1>;
  480. };
  481. &cpsw_port2 {
  482. phy-handle = <&ethphy1>;
  483. phy-mode = "rgmii-txid";
  484. ti,dual-emac-pvid = <2>;
  485. };
  486. &davinci_mdio_sw {
  487. pinctrl-names = "default", "sleep";
  488. pinctrl-0 = <&davinci_mdio_pins_default>;
  489. pinctrl-1 = <&davinci_mdio_pins_sleep>;
  490. ethphy0: ethernet-phy@0 {
  491. reg = <0>;
  492. };
  493. ethphy1: ethernet-phy@1 {
  494. reg = <1>;
  495. };
  496. };
  497. &usb2_phy1 {
  498. phy-supply = <&ldousb_reg>;
  499. };
  500. &usb2_phy2 {
  501. phy-supply = <&ldousb_reg>;
  502. };
  503. &usb1 {
  504. dr_mode = "host";
  505. };
  506. &usb2 {
  507. dr_mode = "host";
  508. };
  509. &mcasp3 {
  510. #sound-dai-cells = <0>;
  511. pinctrl-names = "default", "sleep";
  512. pinctrl-0 = <&mcasp3_pins_default>;
  513. pinctrl-1 = <&mcasp3_pins_sleep>;
  514. status = "okay";
  515. op-mode = <0>; /* MCASP_IIS_MODE */
  516. tdm-slots = <2>;
  517. /* 4 serializers */
  518. serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
  519. 1 2 0 0
  520. >;
  521. };
  522. &gpio3_target {
  523. ti,no-reset-on-init;
  524. };
  525. &gpio2_target {
  526. status = "okay";
  527. ti,no-reset-on-init;
  528. };
  529. &pruss1_mdio {
  530. status = "disabled";
  531. };
  532. &pruss2_mdio {
  533. status = "disabled";
  534. };