am437x-gp-evm.dts 35 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
  4. */
  5. /* AM437x GP EVM */
  6. /dts-v1/;
  7. #include "am4372.dtsi"
  8. #include <dt-bindings/pinctrl/am43xx.h>
  9. #include <dt-bindings/pwm/pwm.h>
  10. #include <dt-bindings/gpio/gpio.h>
  11. / {
  12. model = "TI AM437x GP EVM";
  13. compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43";
  14. aliases {
  15. display0 = &lcd0;
  16. };
  17. chosen {
  18. stdout-path = &uart0;
  19. };
  20. evm_v3_3d: fixedregulator-v3_3d {
  21. compatible = "regulator-fixed";
  22. regulator-name = "evm_v3_3d";
  23. regulator-min-microvolt = <3300000>;
  24. regulator-max-microvolt = <3300000>;
  25. enable-active-high;
  26. };
  27. vtt_fixed: fixedregulator-vtt {
  28. compatible = "regulator-fixed";
  29. regulator-name = "vtt_fixed";
  30. regulator-min-microvolt = <1500000>;
  31. regulator-max-microvolt = <1500000>;
  32. regulator-always-on;
  33. regulator-boot-on;
  34. enable-active-high;
  35. gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
  36. };
  37. vmmcwl_fixed: fixedregulator-mmcwl {
  38. compatible = "regulator-fixed";
  39. regulator-name = "vmmcwl_fixed";
  40. regulator-min-microvolt = <1800000>;
  41. regulator-max-microvolt = <1800000>;
  42. gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>;
  43. enable-active-high;
  44. };
  45. lcd_bl: backlight {
  46. compatible = "pwm-backlight";
  47. pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
  48. brightness-levels = <0 51 53 56 62 75 101 152 255>;
  49. default-brightness-level = <8>;
  50. };
  51. matrix_keypad: matrix_keypad0 {
  52. compatible = "gpio-matrix-keypad";
  53. debounce-delay-ms = <5>;
  54. col-scan-delay-us = <2>;
  55. pinctrl-names = "default", "sleep";
  56. pinctrl-0 = <&matrix_keypad_default>;
  57. pinctrl-1 = <&matrix_keypad_sleep>;
  58. wakeup-source;
  59. row-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH /* Bank0, pin3 */
  60. &gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */
  61. &gpio4 2 GPIO_ACTIVE_HIGH>; /* Bank4, pin2 */
  62. col-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */
  63. &gpio3 20 GPIO_ACTIVE_HIGH>; /* Bank3, pin20 */
  64. linux,keymap = <0x00000201 /* P1 */
  65. 0x00010202 /* P2 */
  66. 0x01000067 /* UP */
  67. 0x0101006a /* RIGHT */
  68. 0x02000069 /* LEFT */
  69. 0x0201006c>; /* DOWN */
  70. };
  71. lcd0: display {
  72. compatible = "osddisplays,osd070t1718-19ts", "panel-dpi";
  73. label = "lcd";
  74. backlight = <&lcd_bl>;
  75. port {
  76. lcd_in: endpoint {
  77. remote-endpoint = <&dpi_out>;
  78. };
  79. };
  80. };
  81. /* fixed 12MHz oscillator */
  82. refclk: oscillator {
  83. #clock-cells = <0>;
  84. compatible = "fixed-clock";
  85. clock-frequency = <12000000>;
  86. };
  87. /* fixed 32k external oscillator clock */
  88. clk_32k_rtc: clk_32k_rtc {
  89. #clock-cells = <0>;
  90. compatible = "fixed-clock";
  91. clock-frequency = <32768>;
  92. };
  93. sound0: sound0 {
  94. compatible = "simple-audio-card";
  95. simple-audio-card,name = "AM437x-GP-EVM";
  96. simple-audio-card,widgets =
  97. "Headphone", "Headphone Jack",
  98. "Line", "Line In";
  99. simple-audio-card,routing =
  100. "Headphone Jack", "HPLOUT",
  101. "Headphone Jack", "HPROUT",
  102. "LINE1L", "Line In",
  103. "LINE1R", "Line In";
  104. simple-audio-card,format = "dsp_b";
  105. simple-audio-card,bitclock-master = <&sound0_master>;
  106. simple-audio-card,frame-master = <&sound0_master>;
  107. simple-audio-card,bitclock-inversion;
  108. simple-audio-card,cpu {
  109. sound-dai = <&mcasp1>;
  110. system-clock-frequency = <12000000>;
  111. };
  112. sound0_master: simple-audio-card,codec {
  113. sound-dai = <&tlv320aic3106>;
  114. system-clock-frequency = <12000000>;
  115. };
  116. };
  117. beeper: beeper {
  118. compatible = "gpio-beeper";
  119. pinctrl-names = "default";
  120. pinctrl-0 = <&beeper_pins_default>;
  121. pinctrl-1 = <&beeper_pins_sleep>;
  122. gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
  123. };
  124. };
  125. &am43xx_pinmux {
  126. pinctrl-names = "default", "sleep";
  127. pinctrl-0 = <&wlan_pins_default &ddr3_vtt_toggle_default &unused_pins &debugss_pins>;
  128. pinctrl-1 = <&wlan_pins_sleep>;
  129. ddr3_vtt_toggle_default: ddr_vtt_toggle_default {
  130. pinctrl-single,pins = <
  131. 0x25C (DS0_PULL_UP_DOWN_EN | PIN_OUTPUT_PULLUP | DS0_FORCE_OFF_MODE | MUX_MODE7) /* spi0_cs0.gpio5_7 */
  132. >;
  133. };
  134. i2c0_pins: i2c0_pins {
  135. pinctrl-single,pins = <
  136. AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
  137. AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
  138. >;
  139. };
  140. i2c1_pins: i2c1_pins {
  141. pinctrl-single,pins = <
  142. AM4372_IOPAD(0x95c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */
  143. AM4372_IOPAD(0x958, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */
  144. >;
  145. };
  146. mmc1_pins: pinmux_mmc1_pins {
  147. pinctrl-single,pins = <
  148. AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
  149. >;
  150. };
  151. ecap0_pins: backlight_pins {
  152. pinctrl-single,pins = <
  153. AM4372_IOPAD(0x964, MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
  154. >;
  155. };
  156. pixcir_ts_pins: pixcir_ts_pins {
  157. pinctrl-single,pins = <
  158. AM4372_IOPAD(0xa64, PIN_INPUT_PULLUP | MUX_MODE7) /* spi2_d0.gpio3_22 */
  159. >;
  160. };
  161. cpsw_default: cpsw_default {
  162. pinctrl-single,pins = <
  163. /* Slave 1 */
  164. AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */
  165. AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */
  166. AM4372_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */
  167. AM4372_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */
  168. AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */
  169. AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */
  170. AM4372_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */
  171. AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
  172. AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */
  173. AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */
  174. AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */
  175. AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */
  176. >;
  177. };
  178. cpsw_sleep: cpsw_sleep {
  179. pinctrl-single,pins = <
  180. /* Slave 1 reset value */
  181. AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
  182. AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
  183. AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
  184. AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
  185. AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
  186. AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
  187. AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
  188. AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
  189. AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
  190. AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
  191. AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
  192. AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
  193. >;
  194. };
  195. davinci_mdio_default: davinci_mdio_default {
  196. pinctrl-single,pins = <
  197. /* MDIO */
  198. AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
  199. AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
  200. >;
  201. };
  202. davinci_mdio_sleep: davinci_mdio_sleep {
  203. pinctrl-single,pins = <
  204. /* MDIO reset value */
  205. AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
  206. AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
  207. >;
  208. };
  209. nand_flash_x8: nand_flash_x8 {
  210. pinctrl-single,pins = <
  211. AM4372_IOPAD(0x800, PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
  212. AM4372_IOPAD(0x804, PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
  213. AM4372_IOPAD(0x808, PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
  214. AM4372_IOPAD(0x80c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
  215. AM4372_IOPAD(0x810, PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
  216. AM4372_IOPAD(0x814, PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
  217. AM4372_IOPAD(0x818, PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
  218. AM4372_IOPAD(0x81c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
  219. AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
  220. AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */
  221. AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
  222. AM4372_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
  223. AM4372_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
  224. AM4372_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
  225. AM4372_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
  226. >;
  227. };
  228. dss_pins: dss_pins {
  229. pinctrl-single,pins = <
  230. AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
  231. AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP | MUX_MODE1)
  232. AM4372_IOPAD(0x828, PIN_OUTPUT_PULLUP | MUX_MODE1)
  233. AM4372_IOPAD(0x82c, PIN_OUTPUT_PULLUP | MUX_MODE1)
  234. AM4372_IOPAD(0x830, PIN_OUTPUT_PULLUP | MUX_MODE1)
  235. AM4372_IOPAD(0x834, PIN_OUTPUT_PULLUP | MUX_MODE1)
  236. AM4372_IOPAD(0x838, PIN_OUTPUT_PULLUP | MUX_MODE1)
  237. AM4372_IOPAD(0x83c, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
  238. AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
  239. AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0)
  240. AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0)
  241. AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0)
  242. AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0)
  243. AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0)
  244. AM4372_IOPAD(0x8b8, PIN_OUTPUT_PULLUP | MUX_MODE0)
  245. AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0)
  246. AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0)
  247. AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0)
  248. AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0)
  249. AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0)
  250. AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0)
  251. AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0)
  252. AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0)
  253. AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
  254. AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
  255. AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
  256. AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
  257. AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
  258. >;
  259. };
  260. display_mux_pins: display_mux_pins {
  261. pinctrl-single,pins = <
  262. /* GPIO 5_8 to select LCD / HDMI */
  263. AM4372_IOPAD(0xa38, PIN_OUTPUT_PULLUP | MUX_MODE7)
  264. >;
  265. };
  266. dcan0_default: dcan0_default_pins {
  267. pinctrl-single,pins = <
  268. AM4372_IOPAD(0x978, PIN_OUTPUT | MUX_MODE2) /* uart1_ctsn.d_can0_tx */
  269. AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_rtsn.d_can0_rx */
  270. >;
  271. };
  272. dcan0_sleep: dcan0_sleep_pins {
  273. pinctrl-single,pins = <
  274. AM4372_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_ctsn.gpio0_12 */
  275. AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_rtsn.gpio0_13 */
  276. >;
  277. };
  278. dcan1_default: dcan1_default_pins {
  279. pinctrl-single,pins = <
  280. AM4372_IOPAD(0x980, PIN_OUTPUT | MUX_MODE2) /* uart1_rxd.d_can1_tx */
  281. AM4372_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.d_can1_rx */
  282. >;
  283. };
  284. dcan1_sleep: dcan1_sleep_pins {
  285. pinctrl-single,pins = <
  286. AM4372_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_rxd.gpio0_14 */
  287. AM4372_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_txd.gpio0_15 */
  288. >;
  289. };
  290. vpfe0_pins_default: vpfe0_pins_default {
  291. pinctrl-single,pins = <
  292. AM4372_IOPAD(0x9b0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/
  293. AM4372_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/
  294. AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/
  295. AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/
  296. AM4372_IOPAD(0x9c8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/
  297. AM4372_IOPAD(0xa08, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/
  298. AM4372_IOPAD(0xa0c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/
  299. AM4372_IOPAD(0xa10, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/
  300. AM4372_IOPAD(0xa14, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/
  301. AM4372_IOPAD(0xa18, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/
  302. AM4372_IOPAD(0xa1c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/
  303. AM4372_IOPAD(0xa20, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/
  304. AM4372_IOPAD(0xa24, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/
  305. >;
  306. };
  307. vpfe0_pins_sleep: vpfe0_pins_sleep {
  308. pinctrl-single,pins = <
  309. AM4372_IOPAD(0x9b0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_hd mode 0*/
  310. AM4372_IOPAD(0x9b4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_vd mode 0*/
  311. AM4372_IOPAD(0x9c0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_pclk mode 0*/
  312. AM4372_IOPAD(0x9c4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data8 mode 0*/
  313. AM4372_IOPAD(0x9c8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data9 mode 0*/
  314. AM4372_IOPAD(0xa08, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data0 mode 0*/
  315. AM4372_IOPAD(0xa0c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data1 mode 0*/
  316. AM4372_IOPAD(0xa10, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data2 mode 0*/
  317. AM4372_IOPAD(0xa14, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data3 mode 0*/
  318. AM4372_IOPAD(0xa18, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data4 mode 0*/
  319. AM4372_IOPAD(0xa1c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data5 mode 0*/
  320. AM4372_IOPAD(0xa20, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data6 mode 0*/
  321. AM4372_IOPAD(0xa24, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data7 mode 0*/
  322. >;
  323. };
  324. vpfe1_pins_default: vpfe1_pins_default {
  325. pinctrl-single,pins = <
  326. AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0*/
  327. AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0*/
  328. AM4372_IOPAD(0x9d4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0*/
  329. AM4372_IOPAD(0x9d8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0*/
  330. AM4372_IOPAD(0x9dC, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0*/
  331. AM4372_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0*/
  332. AM4372_IOPAD(0x9ec, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0*/
  333. AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0*/
  334. AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0*/
  335. AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0*/
  336. AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0*/
  337. AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0*/
  338. AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0*/
  339. >;
  340. };
  341. vpfe1_pins_sleep: vpfe1_pins_sleep {
  342. pinctrl-single,pins = <
  343. AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data9 mode 0*/
  344. AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data8 mode 0*/
  345. AM4372_IOPAD(0x9d4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_hd mode 0*/
  346. AM4372_IOPAD(0x9d8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_vd mode 0*/
  347. AM4372_IOPAD(0x9dc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_pclk mode 0*/
  348. AM4372_IOPAD(0x9e8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data0 mode 0*/
  349. AM4372_IOPAD(0x9ec, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data1 mode 0*/
  350. AM4372_IOPAD(0x9f0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data2 mode 0*/
  351. AM4372_IOPAD(0x9f4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data3 mode 0*/
  352. AM4372_IOPAD(0x9f8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data4 mode 0*/
  353. AM4372_IOPAD(0x9fc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data5 mode 0*/
  354. AM4372_IOPAD(0xa00, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data6 mode 0*/
  355. AM4372_IOPAD(0xa04, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data7 mode 0*/
  356. >;
  357. };
  358. mmc3_pins_default: pinmux_mmc3_pins_default {
  359. pinctrl-single,pins = <
  360. AM4372_IOPAD(0x88c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk */
  361. AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */
  362. AM4372_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0 */
  363. AM4372_IOPAD(0x848, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1 */
  364. AM4372_IOPAD(0x84c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2 */
  365. AM4372_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be1n.mmc2_dat3 */
  366. >;
  367. };
  368. mmc3_pins_sleep: pinmux_mmc3_pins_sleep {
  369. pinctrl-single,pins = <
  370. AM4372_IOPAD(0x88c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_clk.mmc2_clk */
  371. AM4372_IOPAD(0x888, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.mmc2_cmd */
  372. AM4372_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a1.mmc2_dat0 */
  373. AM4372_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a2.mmc2_dat1 */
  374. AM4372_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a3.mmc2_dat2 */
  375. AM4372_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_be1n.mmc2_dat3 */
  376. >;
  377. };
  378. wlan_pins_default: pinmux_wlan_pins_default {
  379. pinctrl-single,pins = <
  380. AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */
  381. AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/
  382. AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/
  383. >;
  384. };
  385. wlan_pins_sleep: pinmux_wlan_pins_sleep {
  386. pinctrl-single,pins = <
  387. AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */
  388. AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/
  389. AM4372_IOPAD(0x840, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/
  390. >;
  391. };
  392. uart3_pins: uart3_pins {
  393. pinctrl-single,pins = <
  394. AM4372_IOPAD(0xa28, PIN_INPUT | MUX_MODE0) /* uart3_rxd.uart3_rxd */
  395. AM4372_IOPAD(0xa2c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_txd.uart3_txd */
  396. AM4372_IOPAD(0xa30, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_ctsn.uart3_ctsn */
  397. AM4372_IOPAD(0xa34, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */
  398. >;
  399. };
  400. mcasp1_pins: mcasp1_pins {
  401. pinctrl-single,pins = <
  402. AM4372_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
  403. AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
  404. AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
  405. AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
  406. >;
  407. };
  408. mcasp1_sleep_pins: mcasp1_sleep_pins {
  409. pinctrl-single,pins = <
  410. AM4372_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7)
  411. AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
  412. AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
  413. AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
  414. >;
  415. };
  416. gpio0_pins: gpio0_pins {
  417. pinctrl-single,pins = <
  418. AM4372_IOPAD(0xa6c, PIN_OUTPUT | MUX_MODE9) /* spi2_cs0.gpio0_23 SEL_eMMCorNANDn */
  419. >;
  420. };
  421. emmc_pins_default: emmc_pins_default {
  422. pinctrl-single,pins = <
  423. AM4372_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
  424. AM4372_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
  425. AM4372_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
  426. AM4372_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
  427. AM4372_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
  428. AM4372_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
  429. AM4372_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
  430. AM4372_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
  431. AM4372_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
  432. AM4372_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
  433. >;
  434. };
  435. emmc_pins_sleep: emmc_pins_sleep {
  436. pinctrl-single,pins = <
  437. AM4372_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad0.gpio1_0 */
  438. AM4372_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad1.gpio1_1 */
  439. AM4372_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad2.gpio1_2 */
  440. AM4372_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad3.gpio1_3 */
  441. AM4372_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */
  442. AM4372_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1_5 */
  443. AM4372_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad6.gpio1_6 */
  444. AM4372_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1_7 */
  445. AM4372_IOPAD(0x880, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn1.gpio1_30 */
  446. AM4372_IOPAD(0x884, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn2.gpio1_31 */
  447. >;
  448. };
  449. beeper_pins_default: beeper_pins_default {
  450. pinctrl-single,pins = <
  451. AM4372_IOPAD(0x9e0, PIN_OUTPUT_PULLUP | MUX_MODE7) /* cam1_field.gpio4_12 */
  452. >;
  453. };
  454. beeper_pins_sleep: beeper_pins_sleep {
  455. pinctrl-single,pins = <
  456. AM4372_IOPAD(0x9e0, PIN_INPUT_PULLDOWN | MUX_MODE7) /* cam1_field.gpio4_12 */
  457. >;
  458. };
  459. unused_pins: unused_pins {
  460. pinctrl-single,pins = <
  461. AM4372_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7)
  462. AM4372_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7)
  463. AM4372_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7)
  464. AM4372_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7)
  465. AM4372_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7)
  466. AM4372_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7)
  467. AM4372_IOPAD(0x950, PIN_INPUT_PULLDOWN | MUX_MODE7)
  468. AM4372_IOPAD(0x990, PIN_INPUT_PULLDOWN | MUX_MODE7)
  469. AM4372_IOPAD(0x994, PIN_INPUT_PULLDOWN | MUX_MODE7)
  470. AM4372_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE7)
  471. AM4372_IOPAD(0x99c, PIN_INPUT_PULLDOWN | MUX_MODE7)
  472. AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE7)
  473. AM4372_IOPAD(0xa3c, PIN_INPUT | PULL_DISABLE | MUX_MODE7)
  474. AM4372_IOPAD(0xa40, PIN_INPUT_PULLDOWN | MUX_MODE7)
  475. AM4372_IOPAD(0xa44, PIN_INPUT_PULLDOWN | MUX_MODE7)
  476. AM4372_IOPAD(0xa48, PIN_INPUT_PULLDOWN | MUX_MODE7)
  477. AM4372_IOPAD(0xa4c, PIN_INPUT_PULLDOWN | MUX_MODE7)
  478. AM4372_IOPAD(0xa50, PIN_INPUT_PULLDOWN | MUX_MODE7)
  479. AM4372_IOPAD(0xa54, PIN_INPUT | PULL_DISABLE | MUX_MODE7)
  480. AM4372_IOPAD(0xa58, PIN_INPUT_PULLDOWN | MUX_MODE7)
  481. AM4372_IOPAD(0xa60, PIN_INPUT | PULL_DISABLE | MUX_MODE7)
  482. AM4372_IOPAD(0xa68, PIN_INPUT_PULLDOWN | MUX_MODE7)
  483. AM4372_IOPAD(0xa70, PIN_INPUT_PULLDOWN | MUX_MODE7)
  484. AM4372_IOPAD(0xa78, PIN_INPUT_PULLDOWN | MUX_MODE7)
  485. AM4372_IOPAD(0xa7c, PIN_INPUT | PULL_DISABLE)
  486. AM4372_IOPAD(0xac8, PIN_INPUT_PULLDOWN)
  487. AM4372_IOPAD(0xad4, PIN_INPUT_PULLDOWN)
  488. AM4372_IOPAD(0xad8, PIN_INPUT_PULLDOWN | MUX_MODE7)
  489. AM4372_IOPAD(0xadc, PIN_INPUT_PULLDOWN | MUX_MODE7)
  490. AM4372_IOPAD(0xae0, PIN_INPUT_PULLDOWN | MUX_MODE7)
  491. AM4372_IOPAD(0xae4, PIN_INPUT_PULLDOWN | MUX_MODE7)
  492. AM4372_IOPAD(0xae8, PIN_INPUT_PULLDOWN | MUX_MODE7)
  493. AM4372_IOPAD(0xaec, PIN_INPUT_PULLDOWN | MUX_MODE7)
  494. AM4372_IOPAD(0xaf0, PIN_INPUT_PULLDOWN | MUX_MODE7)
  495. AM4372_IOPAD(0xaf4, PIN_INPUT_PULLDOWN | MUX_MODE7)
  496. AM4372_IOPAD(0xaf8, PIN_INPUT_PULLDOWN | MUX_MODE7)
  497. AM4372_IOPAD(0xafc, PIN_INPUT_PULLDOWN | MUX_MODE7)
  498. AM4372_IOPAD(0xb00, PIN_INPUT_PULLDOWN | MUX_MODE7)
  499. AM4372_IOPAD(0xb04, PIN_INPUT_PULLDOWN | MUX_MODE7)
  500. AM4372_IOPAD(0xb08, PIN_INPUT_PULLDOWN | MUX_MODE7)
  501. AM4372_IOPAD(0xb0c, PIN_INPUT_PULLDOWN | MUX_MODE7)
  502. AM4372_IOPAD(0xb10, PIN_INPUT_PULLDOWN | MUX_MODE7)
  503. AM4372_IOPAD(0xb14, PIN_INPUT_PULLDOWN | MUX_MODE7)
  504. AM4372_IOPAD(0xb18, PIN_INPUT_PULLDOWN | MUX_MODE7)
  505. >;
  506. };
  507. debugss_pins: pinmux_debugss_pins {
  508. pinctrl-single,pins = <
  509. AM4372_IOPAD(0xa90, PIN_INPUT_PULLDOWN)
  510. AM4372_IOPAD(0xa94, PIN_INPUT_PULLDOWN)
  511. AM4372_IOPAD(0xa98, PIN_INPUT_PULLDOWN)
  512. AM4372_IOPAD(0xa9c, PIN_INPUT_PULLDOWN)
  513. AM4372_IOPAD(0xaa0, PIN_INPUT_PULLDOWN)
  514. AM4372_IOPAD(0xaa4, PIN_INPUT_PULLDOWN)
  515. AM4372_IOPAD(0xaa8, PIN_INPUT_PULLDOWN)
  516. >;
  517. };
  518. uart0_pins_default: uart0_pins_default {
  519. pinctrl-single,pins = <
  520. AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_ctsn.uart0_ctsn */
  521. AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_rtsn.uart0_rtsn */
  522. AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */
  523. AM4372_IOPAD(0x974, PIN_INPUT | PULL_DISABLE | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */
  524. >;
  525. };
  526. uart0_pins_sleep: uart0_pins_sleep {
  527. pinctrl-single,pins = <
  528. AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* uart0_ctsn.uart0_ctsn */
  529. AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* uart0_rtsn.uart0_rtsn */
  530. AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */
  531. AM4372_IOPAD(0x974, PIN_INPUT_PULLDOWN | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */
  532. >;
  533. };
  534. matrix_keypad_default: matrix_keypad_default {
  535. pinctrl-single,pins = <
  536. AM4372_IOPAD(0x9a4, PIN_OUTPUT | MUX_MODE7)
  537. AM4372_IOPAD(0x9a8, PIN_OUTPUT | MUX_MODE7)
  538. AM4372_IOPAD(0x9ac, PIN_INPUT | PULL_DISABLE | MUX_MODE9)
  539. AM4372_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE0)
  540. >;
  541. };
  542. matrix_keypad_sleep: matrix_keypad_sleep {
  543. pinctrl-single,pins = <
  544. AM4372_IOPAD(0x9a4, PULL_UP | MUX_MODE7)
  545. AM4372_IOPAD(0x9a8, PULL_UP | MUX_MODE7)
  546. AM4372_IOPAD(0x9ac, PIN_INPUT | PULL_DISABLE | MUX_MODE9)
  547. AM4372_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE0)
  548. >;
  549. };
  550. };
  551. &uart0 {
  552. status = "okay";
  553. pinctrl-names = "default", "sleep";
  554. pinctrl-0 = <&uart0_pins_default>;
  555. pinctrl-1 = <&uart0_pins_sleep>;
  556. };
  557. &i2c0 {
  558. status = "okay";
  559. pinctrl-names = "default";
  560. pinctrl-0 = <&i2c0_pins>;
  561. clock-frequency = <100000>;
  562. tps65218: tps65218@24 {
  563. reg = <0x24>;
  564. compatible = "ti,tps65218";
  565. interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* NMIn */
  566. interrupt-controller;
  567. #interrupt-cells = <2>;
  568. dcdc1: regulator-dcdc1 {
  569. regulator-name = "vdd_core";
  570. regulator-min-microvolt = <912000>;
  571. regulator-max-microvolt = <1144000>;
  572. regulator-boot-on;
  573. regulator-always-on;
  574. };
  575. dcdc2: regulator-dcdc2 {
  576. regulator-name = "vdd_mpu";
  577. regulator-min-microvolt = <912000>;
  578. regulator-max-microvolt = <1378000>;
  579. regulator-boot-on;
  580. regulator-always-on;
  581. };
  582. dcdc3: regulator-dcdc3 {
  583. regulator-name = "vdcdc3";
  584. regulator-boot-on;
  585. regulator-always-on;
  586. regulator-state-mem {
  587. regulator-on-in-suspend;
  588. };
  589. regulator-state-disk {
  590. regulator-off-in-suspend;
  591. };
  592. };
  593. dcdc5: regulator-dcdc5 {
  594. regulator-name = "v1_0bat";
  595. regulator-min-microvolt = <1000000>;
  596. regulator-max-microvolt = <1000000>;
  597. regulator-boot-on;
  598. regulator-always-on;
  599. regulator-state-mem {
  600. regulator-on-in-suspend;
  601. };
  602. };
  603. dcdc6: regulator-dcdc6 {
  604. regulator-name = "v1_8bat";
  605. regulator-min-microvolt = <1800000>;
  606. regulator-max-microvolt = <1800000>;
  607. regulator-boot-on;
  608. regulator-always-on;
  609. regulator-state-mem {
  610. regulator-on-in-suspend;
  611. };
  612. };
  613. ldo1: regulator-ldo1 {
  614. regulator-min-microvolt = <1800000>;
  615. regulator-max-microvolt = <1800000>;
  616. regulator-boot-on;
  617. regulator-always-on;
  618. };
  619. };
  620. ov2659@30 {
  621. compatible = "ovti,ov2659";
  622. reg = <0x30>;
  623. clocks = <&refclk 0>;
  624. clock-names = "xvclk";
  625. port {
  626. ov2659_0: endpoint {
  627. remote-endpoint = <&vpfe1_ep>;
  628. link-frequencies = /bits/ 64 <70000000>;
  629. };
  630. };
  631. };
  632. };
  633. &i2c1 {
  634. status = "okay";
  635. pinctrl-names = "default";
  636. pinctrl-0 = <&i2c1_pins>;
  637. pixcir_ts@5c {
  638. compatible = "pixcir,pixcir_tangoc";
  639. pinctrl-names = "default";
  640. pinctrl-0 = <&pixcir_ts_pins>;
  641. reg = <0x5c>;
  642. attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
  643. /*
  644. * 0x264 represents the offset of padconf register of
  645. * gpio3_22 from am43xx_pinmux base.
  646. */
  647. interrupts-extended = <&gpio3 22 IRQ_TYPE_EDGE_FALLING>,
  648. <&am43xx_pinmux 0x264>;
  649. interrupt-names = "tsc", "wakeup";
  650. touchscreen-size-x = <1024>;
  651. touchscreen-size-y = <600>;
  652. wakeup-source;
  653. };
  654. ov2659@30 {
  655. compatible = "ovti,ov2659";
  656. reg = <0x30>;
  657. clocks = <&refclk 0>;
  658. clock-names = "xvclk";
  659. port {
  660. ov2659_1: endpoint {
  661. remote-endpoint = <&vpfe0_ep>;
  662. link-frequencies = /bits/ 64 <70000000>;
  663. };
  664. };
  665. };
  666. tlv320aic3106: tlv320aic3106@1b {
  667. #sound-dai-cells = <0>;
  668. compatible = "ti,tlv320aic3106";
  669. reg = <0x1b>;
  670. status = "okay";
  671. /* Regulators */
  672. IOVDD-supply = <&evm_v3_3d>; /* V3_3D -> <tps63031> EN: V1_8D -> VBAT */
  673. AVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */
  674. DRVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */
  675. DVDD-supply = <&ldo1>; /* V1_8D -> LDO1 */
  676. };
  677. };
  678. &epwmss0 {
  679. status = "okay";
  680. };
  681. &tscadc {
  682. status = "okay";
  683. adc {
  684. ti,adc-channels = <0 1 2 3 4 5 6 7>;
  685. };
  686. };
  687. &magadc {
  688. status = "okay";
  689. adc {
  690. ti,adc-channels = <0 1 2 3 4 5 6 7>;
  691. };
  692. };
  693. &ecap0 {
  694. status = "okay";
  695. pinctrl-names = "default";
  696. pinctrl-0 = <&ecap0_pins>;
  697. };
  698. &gpio0 {
  699. pinctrl-names = "default";
  700. pinctrl-0 = <&gpio0_pins>;
  701. status = "okay";
  702. sel-emmc-nand-hog {
  703. gpio-hog;
  704. gpios = <23 GPIO_ACTIVE_HIGH>;
  705. /* SelEMMCorNAND selects between eMMC and NAND:
  706. * Low: NAND
  707. * High: eMMC
  708. * When changing this line make sure the newly
  709. * selected device node is enabled and the previously
  710. * selected device node is disabled.
  711. */
  712. output-low;
  713. line-name = "SelEMMCorNAND";
  714. };
  715. };
  716. &gpio1 {
  717. status = "okay";
  718. };
  719. &gpio3 {
  720. status = "okay";
  721. };
  722. &gpio4 {
  723. status = "okay";
  724. };
  725. &gpio5_target {
  726. ti,no-reset-on-init;
  727. };
  728. &gpio5 {
  729. pinctrl-names = "default";
  730. pinctrl-0 = <&display_mux_pins>;
  731. status = "okay";
  732. sel-lcd-hdmi-hog {
  733. /*
  734. * SelLCDorHDMI selects between display and audio paths:
  735. * Low: HDMI display with audio via HDMI
  736. * High: LCD display with analog audio via aic3111 codec
  737. */
  738. gpio-hog;
  739. gpios = <8 GPIO_ACTIVE_HIGH>;
  740. output-high;
  741. line-name = "SelLCDorHDMI";
  742. };
  743. };
  744. &mmc1 {
  745. status = "okay";
  746. vmmc-supply = <&evm_v3_3d>;
  747. bus-width = <4>;
  748. pinctrl-names = "default";
  749. pinctrl-0 = <&mmc1_pins>;
  750. cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
  751. };
  752. /* eMMC sits on mmc2 */
  753. &mmc2 {
  754. /*
  755. * When enabling eMMC, disable GPMC/NAND and set
  756. * SelEMMCorNAND to output-high
  757. */
  758. status = "disabled";
  759. vmmc-supply = <&evm_v3_3d>;
  760. bus-width = <8>;
  761. pinctrl-names = "default", "sleep";
  762. pinctrl-0 = <&emmc_pins_default>;
  763. pinctrl-1 = <&emmc_pins_sleep>;
  764. non-removable;
  765. };
  766. &mmc3 {
  767. status = "okay";
  768. /* these are on the crossbar and are outlined in the
  769. xbar-event-map element */
  770. dmas = <&edma_xbar 30 0 1>,
  771. <&edma_xbar 31 0 2>;
  772. dma-names = "tx", "rx";
  773. vmmc-supply = <&vmmcwl_fixed>;
  774. bus-width = <4>;
  775. pinctrl-names = "default", "sleep";
  776. pinctrl-0 = <&mmc3_pins_default>;
  777. pinctrl-1 = <&mmc3_pins_sleep>;
  778. cap-power-off-card;
  779. keep-power-in-suspend;
  780. non-removable;
  781. #address-cells = <1>;
  782. #size-cells = <0>;
  783. wlcore: wlcore@0 {
  784. compatible = "ti,wl1835";
  785. reg = <2>;
  786. interrupt-parent = <&gpio1>;
  787. interrupts = <23 IRQ_TYPE_EDGE_RISING>;
  788. };
  789. };
  790. &uart3 {
  791. status = "okay";
  792. pinctrl-names = "default";
  793. pinctrl-0 = <&uart3_pins>;
  794. };
  795. &usb2_phy1 {
  796. status = "okay";
  797. };
  798. &usb1 {
  799. dr_mode = "otg";
  800. status = "okay";
  801. };
  802. &usb2_phy2 {
  803. status = "okay";
  804. };
  805. &usb2 {
  806. dr_mode = "host";
  807. status = "okay";
  808. };
  809. &mac_sw {
  810. pinctrl-names = "default", "sleep";
  811. pinctrl-0 = <&cpsw_default>;
  812. pinctrl-1 = <&cpsw_sleep>;
  813. status = "okay";
  814. };
  815. &davinci_mdio_sw {
  816. pinctrl-names = "default", "sleep";
  817. pinctrl-0 = <&davinci_mdio_default>;
  818. pinctrl-1 = <&davinci_mdio_sleep>;
  819. ethphy0: ethernet-phy@0 {
  820. reg = <0>;
  821. };
  822. };
  823. &cpsw_port1 {
  824. phy-handle = <&ethphy0>;
  825. phy-mode = "rgmii-rxid";
  826. ti,dual-emac-pvid = <1>;
  827. };
  828. &cpsw_port2 {
  829. status = "disabled";
  830. };
  831. &elm {
  832. status = "okay";
  833. };
  834. &gpmc {
  835. /*
  836. * When enabling GPMC, disable eMMC and set
  837. * SelEMMCorNAND to output-low
  838. */
  839. status = "okay";
  840. pinctrl-names = "default";
  841. pinctrl-0 = <&nand_flash_x8>;
  842. ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */
  843. nand@0,0 {
  844. compatible = "ti,omap2-nand";
  845. reg = <0 0 4>; /* device IO registers */
  846. interrupt-parent = <&gpmc>;
  847. interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
  848. <1 IRQ_TYPE_NONE>; /* termcount */
  849. rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
  850. ti,nand-xfer-type = "prefetch-dma";
  851. ti,nand-ecc-opt = "bch16";
  852. ti,elm-id = <&elm>;
  853. nand-bus-width = <8>;
  854. gpmc,device-width = <1>;
  855. gpmc,sync-clk-ps = <0>;
  856. gpmc,cs-on-ns = <0>;
  857. gpmc,cs-rd-off-ns = <40>;
  858. gpmc,cs-wr-off-ns = <40>;
  859. gpmc,adv-on-ns = <0>;
  860. gpmc,adv-rd-off-ns = <25>;
  861. gpmc,adv-wr-off-ns = <25>;
  862. gpmc,we-on-ns = <0>;
  863. gpmc,we-off-ns = <20>;
  864. gpmc,oe-on-ns = <3>;
  865. gpmc,oe-off-ns = <30>;
  866. gpmc,access-ns = <30>;
  867. gpmc,rd-cycle-ns = <40>;
  868. gpmc,wr-cycle-ns = <40>;
  869. gpmc,bus-turnaround-ns = <0>;
  870. gpmc,cycle2cycle-delay-ns = <0>;
  871. gpmc,clk-activation-ns = <0>;
  872. gpmc,wr-access-ns = <40>;
  873. gpmc,wr-data-mux-bus-ns = <0>;
  874. /* MTD partition table */
  875. /* All SPL-* partitions are sized to minimal length
  876. * which can be independently programmable. For
  877. * NAND flash this is equal to size of erase-block */
  878. #address-cells = <1>;
  879. #size-cells = <1>;
  880. partition@0 {
  881. label = "NAND.SPL";
  882. reg = <0x00000000 0x00040000>;
  883. };
  884. partition@1 {
  885. label = "NAND.SPL.backup1";
  886. reg = <0x00040000 0x00040000>;
  887. };
  888. partition@2 {
  889. label = "NAND.SPL.backup2";
  890. reg = <0x00080000 0x00040000>;
  891. };
  892. partition@3 {
  893. label = "NAND.SPL.backup3";
  894. reg = <0x000c0000 0x00040000>;
  895. };
  896. partition@4 {
  897. label = "NAND.u-boot-spl-os";
  898. reg = <0x00100000 0x00080000>;
  899. };
  900. partition@5 {
  901. label = "NAND.u-boot";
  902. reg = <0x00180000 0x00100000>;
  903. };
  904. partition@6 {
  905. label = "NAND.u-boot-env";
  906. reg = <0x00280000 0x00040000>;
  907. };
  908. partition@7 {
  909. label = "NAND.u-boot-env.backup1";
  910. reg = <0x002c0000 0x00040000>;
  911. };
  912. partition@8 {
  913. label = "NAND.kernel";
  914. reg = <0x00300000 0x00700000>;
  915. };
  916. partition@9 {
  917. label = "NAND.file-system";
  918. reg = <0x00a00000 0x1f600000>;
  919. };
  920. };
  921. };
  922. &dss {
  923. status = "okay";
  924. pinctrl-names = "default";
  925. pinctrl-0 = <&dss_pins>;
  926. port {
  927. dpi_out: endpoint {
  928. remote-endpoint = <&lcd_in>;
  929. data-lines = <24>;
  930. };
  931. };
  932. };
  933. &dcan0 {
  934. pinctrl-names = "default", "sleep";
  935. pinctrl-0 = <&dcan0_default>;
  936. pinctrl-1 = <&dcan0_sleep>;
  937. status = "okay";
  938. };
  939. &dcan1 {
  940. pinctrl-names = "default", "sleep";
  941. pinctrl-0 = <&dcan1_default>;
  942. pinctrl-1 = <&dcan1_sleep>;
  943. status = "okay";
  944. };
  945. &vpfe0 {
  946. status = "okay";
  947. pinctrl-names = "default", "sleep";
  948. pinctrl-0 = <&vpfe0_pins_default>;
  949. pinctrl-1 = <&vpfe0_pins_sleep>;
  950. port {
  951. vpfe0_ep: endpoint {
  952. remote-endpoint = <&ov2659_1>;
  953. ti,am437x-vpfe-interface = <0>;
  954. bus-width = <8>;
  955. hsync-active = <0>;
  956. vsync-active = <0>;
  957. };
  958. };
  959. };
  960. &vpfe1 {
  961. status = "okay";
  962. pinctrl-names = "default", "sleep";
  963. pinctrl-0 = <&vpfe1_pins_default>;
  964. pinctrl-1 = <&vpfe1_pins_sleep>;
  965. port {
  966. vpfe1_ep: endpoint {
  967. remote-endpoint = <&ov2659_0>;
  968. ti,am437x-vpfe-interface = <0>;
  969. bus-width = <8>;
  970. hsync-active = <0>;
  971. vsync-active = <0>;
  972. };
  973. };
  974. };
  975. &mcasp1 {
  976. #sound-dai-cells = <0>;
  977. pinctrl-names = "default", "sleep";
  978. pinctrl-0 = <&mcasp1_pins>;
  979. pinctrl-1 = <&mcasp1_sleep_pins>;
  980. status = "okay";
  981. op-mode = <0>; /* MCASP_IIS_MODE */
  982. tdm-slots = <2>;
  983. /* 4 serializers */
  984. serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
  985. 0 0 1 2
  986. >;
  987. tx-num-evt = <32>;
  988. rx-num-evt = <32>;
  989. };
  990. &rtc {
  991. clocks = <&clk_32k_rtc>, <&clk_32768_ck>;
  992. clock-names = "ext-clk", "int-clk";
  993. status = "okay";
  994. };
  995. &cpu {
  996. cpu0-supply = <&dcdc2>;
  997. };
  998. &wkup_m3_ipc {
  999. ti,set-io-isolation;
  1000. firmware-name = "am43x-evm-scale-data.bin";
  1001. };
  1002. &pruss1_mdio {
  1003. status = "disabled";
  1004. };