am3517-som.dtsi 6.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2016 Derald D. Woods <[email protected]>
  4. *
  5. * Based on am3517-evm.dts
  6. */
  7. / {
  8. cpus {
  9. cpu@0 {
  10. cpu0-supply = <&vdd_core_reg>;
  11. };
  12. };
  13. wl12xx_buffer: wl12xx_buf {
  14. compatible = "regulator-fixed";
  15. regulator-name = "wl1271_buf";
  16. regulator-min-microvolt = <1800000>;
  17. regulator-max-microvolt = <1800000>;
  18. pinctrl-names = "default";
  19. pinctrl-0 = <&wl12xx_buffer_pins>;
  20. gpio = <&gpio5 1 GPIO_ACTIVE_LOW>; /* gpio 129 */
  21. regulator-always-on;
  22. vin-supply = <&vdd_1v8_reg>;
  23. };
  24. wl12xx_vmmc2: wl12xx_vmmc2 {
  25. compatible = "regulator-fixed";
  26. regulator-name = "vwl1271";
  27. regulator-min-microvolt = <1800000>;
  28. regulator-max-microvolt = <1800000>;
  29. pinctrl-names = "default";
  30. pinctrl-0 = <&wl12xx_wkup_pins>;
  31. gpio = <&gpio1 3 GPIO_ACTIVE_HIGH >; /* gpio 3 */
  32. startup-delay-us = <70000>;
  33. enable-active-high;
  34. regulator-always-on;
  35. vin-supply = <&wl12xx_buffer>;
  36. };
  37. };
  38. &gpmc {
  39. ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */
  40. nand@0,0 {
  41. compatible = "ti,omap2-nand";
  42. linux,mtd-name = "micron,mt29f4g16abchch";
  43. reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
  44. nand-bus-width = <16>;
  45. ti,nand-ecc-opt = "bch8";
  46. gpmc,sync-clk-ps = <0>;
  47. gpmc,cs-on-ns = <0>;
  48. gpmc,cs-rd-off-ns = <44>;
  49. gpmc,cs-wr-off-ns = <44>;
  50. gpmc,adv-on-ns = <6>;
  51. gpmc,adv-rd-off-ns = <34>;
  52. gpmc,adv-wr-off-ns = <44>;
  53. gpmc,we-off-ns = <40>;
  54. gpmc,oe-off-ns = <54>;
  55. gpmc,access-ns = <64>;
  56. gpmc,rd-cycle-ns = <82>;
  57. gpmc,wr-cycle-ns = <82>;
  58. gpmc,wr-access-ns = <40>;
  59. gpmc,wr-data-mux-bus-ns = <0>;
  60. gpmc,device-width = <2>;
  61. #address-cells = <1>;
  62. #size-cells = <1>;
  63. };
  64. };
  65. &i2c1 {
  66. pinctrl-names = "default";
  67. pinctrl-0 = <&i2c1_pins>;
  68. clock-frequency = <400000>;
  69. s35390a: s35390a@30 {
  70. compatible = "sii,s35390a";
  71. reg = <0x30>;
  72. pinctrl-names = "default";
  73. pinctrl-0 = <&rtc_pins>;
  74. interrupts-extended = <&gpio2 23 IRQ_TYPE_EDGE_FALLING>; /* gpio_55 */
  75. };
  76. tps: tps65023@48 {
  77. compatible = "ti,tps65023";
  78. reg = <0x48>;
  79. regulators {
  80. vdd_core_reg: VDCDC1 {
  81. regulator-name = "vdd_core";
  82. regulator-always-on;
  83. regulator-min-microvolt = <1200000>;
  84. regulator-max-microvolt = <1200000>;
  85. };
  86. vdd_io_reg: VDCDC2 {
  87. regulator-name = "vdd_io";
  88. regulator-always-on;
  89. regulator-min-microvolt = <3300000>;
  90. regulator-max-microvolt = <3300000>;
  91. };
  92. vdd_1v8_reg: VDCDC3 {
  93. regulator-name = "vdd_1v8";
  94. regulator-always-on;
  95. regulator-min-microvolt = <1800000>;
  96. regulator-max-microvolt = <1800000>;
  97. };
  98. vdd_usb18_reg: LDO1 {
  99. regulator-name = "vdd_usb18";
  100. regulator-always-on;
  101. regulator-min-microvolt = <1800000>;
  102. regulator-max-microvolt = <1800000>;
  103. };
  104. vdd_usb33_reg: LDO2 {
  105. regulator-name = "vdd_usb33";
  106. regulator-always-on;
  107. regulator-min-microvolt = <3300000>;
  108. regulator-max-microvolt = <3300000>;
  109. };
  110. };
  111. };
  112. touchscreen: tsc2004@4b {
  113. compatible = "ti,tsc2004";
  114. reg = <0x4b>;
  115. vio-supply = <&vdd_io_reg>;
  116. pinctrl-names = "default";
  117. pinctrl-0 = <&tsc2004_pins>;
  118. interrupts-extended = <&gpio3 1 IRQ_TYPE_EDGE_RISING>; /* gpio_65 */
  119. touchscreen-fuzz-x = <4>;
  120. touchscreen-fuzz-y = <7>;
  121. touchscreen-fuzz-pressure = <2>;
  122. touchscreen-size-x = <480>;
  123. touchscreen-size-y = <272>;
  124. touchscreen-max-pressure = <2048>;
  125. ti,x-plate-ohms = <280>;
  126. ti,esd-recovery-timeout-ms = <8000>;
  127. };
  128. };
  129. &mmc2 {
  130. interrupts-extended = <&intc 86 /* &omap3_pmx_core 0x12c */>;
  131. status = "okay";
  132. pinctrl-names = "default";
  133. pinctrl-0 = <&mmc2_pins>;
  134. vmmc-supply = <&wl12xx_vmmc2>;
  135. non-removable;
  136. bus-width = <4>;
  137. cap-power-off-card;
  138. #address-cells = <1>;
  139. #size-cells = <0>;
  140. wlcore: wlcore@2 {
  141. compatible = "ti,wl1271";
  142. reg = <2>;
  143. interrupt-parent = <&gpio6>;
  144. interrupts = <10 IRQ_TYPE_EDGE_RISING>; /* gpio_170 */
  145. ref-clock-frequency = <26000000>;
  146. tcxo-clock-frequency = <26000000>;
  147. };
  148. };
  149. &uart2 {
  150. pinctrl-names = "default";
  151. pinctrl-0 = <&uart2_pins>;
  152. bluetooth {
  153. compatible = "ti,wl1271-st";
  154. enable-gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; /* gpio 56 */
  155. max-speed = <3000000>;
  156. };
  157. };
  158. &omap3_pmx_core {
  159. i2c1_pins: pinmux_i2c1_pins {
  160. pinctrl-single,pins = <
  161. OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */
  162. OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */
  163. >;
  164. };
  165. wl12xx_buffer_pins: pinmux_wl12xx_buffer_pins {
  166. pinctrl-single,pins = <
  167. OMAP3_CORE1_IOPAD(0x2156, PIN_OUTPUT | MUX_MODE4) /* mmc1_dat7.gpio_129 */
  168. >;
  169. };
  170. mmc2_pins: pinmux_mmc2_pins {
  171. pinctrl-single,pins = <
  172. OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_clk.mmc2_clk */
  173. OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_cmd.mmc2_cmd */
  174. OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat0.mmc2_dat0 */
  175. OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat1.mmc2_dat1 */
  176. OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat2.mmc2_dat2 */
  177. OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat3.mmc2_dat3 */
  178. OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat4.mmc2_dir_dat0 */
  179. OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat5.mmc2_dir_dat1 */
  180. OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat6.mmc2_dir_cmd */
  181. OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* mmc2_dat7.mmc2_clkin */
  182. OMAP3_CORE1_IOPAD(0x21c6, PIN_INPUT_PULLUP | MUX_MODE4) /* hdq_sio.gpio_170 */
  183. >;
  184. };
  185. rtc_pins: pinmux_rtc_pins {
  186. pinctrl-single,pins = <
  187. OMAP3_CORE1_IOPAD(0x20b6, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_ncs4.gpio_55 */
  188. >;
  189. };
  190. tsc2004_pins: pinmux_tsc2004_pins {
  191. pinctrl-single,pins = <
  192. OMAP3_CORE1_IOPAD(0x20d2, PIN_INPUT | MUX_MODE4) /* gpmc_wait3.gpio_65 */
  193. >;
  194. };
  195. uart2_pins: pinmux_uart2_pins {
  196. pinctrl-single,pins = <
  197. OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts */
  198. OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT_PULLUP | MUX_MODE0) /* uart2_rts */
  199. OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx */
  200. OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx */
  201. OMAP3_CORE1_IOPAD(0x20b8, PIN_INPUT | MUX_MODE0) /* gpio_56 */
  202. >;
  203. };
  204. };
  205. &omap3_pmx_wkup {
  206. wl12xx_wkup_pins: pinmux_wl12xx_wkup_pins {
  207. pinctrl-single,pins = <
  208. OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */
  209. >;
  210. };
  211. };